Functional Overview
41
June 2004
SPRS257
Figure 3
6 shows how the interrupts are multiplexed using the PIE block. Eight PIE block interrupts are
grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96
possible interrupts. On R281x, 45 of these are used by peripherals as shown in Table 3
8.
INT12
MUX
INT11
INT2
INT1
CPU
(Enable)
(Flag)
INTx
INTx.8
PIEIERx(8:1)
PIEIFRx(8:1)
MUX
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
From
Peripherals or
External
Interrupts
(Enable)
(Flag)
IER(12:1)
IFR(12:1)
Global
Enable
INTM
1
0
PIEACKx
(Enable/Flag)
Figure 3
6. Multiplexing of Interrupts Using the PIE Block
Table 3
8. PIE Peripheral Interrupts
CPU
PIE INTERRUPTS
INTx.5
INTERRUPTS
INTx.8
WAKEINT
(LPM/WD)
INTx.7
TINT0
(TIMER 0)
T1OFINT
(EV-A)
CAPINT3
(EV-A)
T3OFINT
(EV-B)
CAPINT6
(EV-B)
INTx.6
ADCINT
(ADC)
T1UFINT
(EV-A)
CAPINT2
(EV-A)
T3UFINT
(EV-B)
CAPINT5
(EV-B)
MXINT
(McBSP)
reserved
reserved
ECAN1INT
(CAN)
reserved
reserved
reserved
INTx.4
INTx.3
INTx.2
PDPINTB
(EV-B)
CMP2INT
(EV-A)
T2CINT
(EV-A)
CMP5INT
(EV-B)
T4CINT
(EV-B)
SPITXINTA
(SPI)
reserved
reserved
SCITXINTA
(SCI-A)
reserved
reserved
reserved
INTx.1
PDPINTA
(EV-A)
CMP1INT
(EV-A)
T2PINT
(EV-A)
CMP4INT
(EV-B)
T4PINT
(EV-B)
SPIRXINTA
(SPI)
reserved
reserved
SCIRXINTA
(SCI-A)
reserved
reserved
reserved
INT1
XINT2
XINT1
reserved
INT2
reserved
T1CINT
(EV-A)
CAPINT1
(EV-A)
T3CINT
(EV-B)
CAPINT4
(EV-B)
MRINT
(McBSP)
reserved
reserved
ECAN0INT
(CAN)
reserved
reserved
reserved
T1PINT
(EV-A)
T2OFINT
(EV-A)
T3PINT
(EV-B)
T4OFINT
(EV-B)
CMP3INT
(EV-A)
T2UFINT
(EV-A)
CMP6INT
(EV-B)
T4UFINT
(EV-B)
INT3
reserved
INT4
reserved
INT5
reserved
INT6
reserved
reserved
reserved
reserved
INT7
INT8
reserved
reserved
reserved
reserved
reserved
reserved
SCITXINTB
(SCI-B)
reserved
reserved
reserved
reserved
reserved
SCIRXINTB
(SCI-B)
reserved
reserved
reserved
INT9
reserved
reserved
INT10
INT11
INT12
reserved
reserved
reserved
reserved
reserved
reserved
Out of the 96 possible interrupts, 45 interrupts are currently used. the remaining interrupts are reserved for future devices. However, these
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level.
A