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参数资料
型号： TMX320F2812ZHHS
厂商： Texas Instruments, Inc.
元件分类： 数字信号处理
英文描述： TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述： TMS320R2811，TMS320R2812数字信号处理器
文件页数： 100/147页
文件大小： 2021K
代理商： TMX320F2812ZHHS
Electrical Specifications
100
June 2004
SPRS257
6.16
Event Manager Interface
6.16.1
PWM Timing
PWM refers to all PWM outputs on EVA and EVB.
Table 6
12. PWM Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
t
w(PWM)§
t
d(PWM)XCO
See the GPIO output timing for fall/rise times for PWM pins.
PWM pin toggling frequency is limited by the GPIO output buffer switching frequency (20 MHz).
§
PWM outputs may be 100%, 0%, or increments of t
c(HCO)
with respect to the PWM period.
Pulse duration, PWMx output high/low
25
ns
Delay time, XCLKOUT high to PWMx output switching
XCLKOUT = SYSCLKOUT/4
10
ns
Table 6
13. Timer and Capture Unit Timing Requirements
#
MIN
MAX
UNIT
t
w(TDIR)
Pulse duration TDIRx low/high
Pulse duration, TDIRx low/high
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
2 * t
c(SCO)
1 * t
c(SCO)
+ IQT
||
2 * t
c(SCO)
1 * t
c(SCO)
+ IQT
||
40
cycles
t
w(CAP)
Pulse duration CAPx input low/high
Pulse duration, CAPx input low/high
cycles
t
w(TCLKINL)
t
w(TCLKINH)
t
c(TCLKIN)
The QUALPRD bit field value can range from 0 (no qualification) through 0xFF (510 SYSCLKOUT cycles). The qualification sampling period is
2n SYSCLKOUT cycles, where “n” is the value stored in the QUALPRD bit field. As an example, when QUALPRD = 1, the qualification sampling
period is 1 x 2 = 2 SYSCLKOUT cycles (i.e., the input is sampled every 2 SYSCLKOUT cycles). Six such samples will be taken over five sampling
windows, each window being 2n SYSCLKOUT cycles. For QUALPRD = 1, the minimum width that is needed is 5 x 2 = 10 SYSCLKOUT cycles.
However, since the external signal is driven asynchronously, a 11-SYSCLKOUT-wide pulse ensures reliable recognition.
#
Maximum input frequency to the QEP = min[HSPCLK/2, 20 MHz]
||
Input Qualification Time (IQT) = [5 x QUALPRD x 2] * t
c(SCO)
Pulse duration, TCLKINx low as a percentage of TCLKINx cycle time
60
%
Pulse duration, TCLKINx high as a percentage of TCLKINx cycle time
40
60
%
Cycle time, TCLKINx
4 * t
c(HCO)
ns
t
w(PWM)
t
d(PWM)XCO
PWMx
XCLKOUT
XCLKOUT = SYSCLKOUT
Figure 6
13. PWM Output Timing
XCLKOUT
t
w(TDIR)
TDIRx
XCLKOUT = SYSCLKOUT
Figure 6
14. TDIRx Timing
A
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