TPS2393A
SLUS610 JULY 2004
13
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DETAILED DESCRIPTION
The TPS2393A operates directly from the input supply (nominal 48 VDC) rail. The VIN pin connects to the
negative voltage rail, and the RTN pin connects to the supply return. Internal regulators convert input power to
the supply levels required by the device circuitry. An input UVLO circuit holds the GATE output low until the
supply voltage reaches a nominal 16-V level, regardless of the status of all other control inputs. A block of
comparators monitors input supply voltage and other output enable conditions. As shown in Figure 24, the
status of these five comparators is AND’d together in order to enable turning on power to the load. Two precision
comparators monitor the voltage levels at the UVLO and OVLO pins. Typically, these pins are driven with a
divided-down sample of the supply voltage to establish the UVLO and OVLO trip thresholds for the circuit. The
UVLO input must be above the internal 1.4-V reference, and the OVLO pin must remain below the reference
voltage to enable the load. Both of these inputs are provided with a small, 10-
A pull-up source, which is
switched to the input pin whenever the associated comparator is tripped. These current sources provide a
mechanism for user-programming of the amount of hysteresis for the UVLO and OVLO thresholds.
The same comparator circuit is also available at the EN pin, providing a third precision input. A switched pull-up
is also available at this pin for hysteresis programming. Alternatively, this input can be used as a logic enable
command, with a nominal 1.4-V logic threshold.
The INSA and INSB pins provide an optional insertion detection function to the hot swap circuit. Both these pins
must be pulled low, below 1.0 -V to enable a load start-up. Internal pull-ups at these inputs maintain a HI logic
level (about 6.5 V) at the device pins when floating. This eliminates the need for additional external components
to maintain the HI logic level during insertion and extraction events. An external mechanism for pulling these
inputs low, typically though backplane connections to the low-side rail, starts a timer to hold off power up during
contact bounce. Loss of either input assertion resets the timer. Once the inserted condition is latched with
expiration of the 6-ms timer, the timer is then used to filter the inputs against transient spikes due to supply noise
and glitches in the power distribution.
Once the device is enabled (internal EN_A signal asserted), the GATE output pull-down is turned off, and the
linear control amplifier (LCA) is enabled. A current source in the ramp generator block begins charging an
external capacitor connected between the IRAMP and VIN pins. The resultant voltage ramp at the IRAMP pin
is scaled by a factor of 1/100, and applied to the non-inverting input of the LCA (the VLIM signal). Load current
magnitude information at the ISENS pin is applied to the inverting input. This sense voltage is developed by
connecting the current sense resistor between ISENS and VIN. As the external FET begins to conduct, the
LCA slews its gate to force the ISENS voltage to track the internal reference (VLIM). Consequently, the load
current slew rate tracks the linear voltage ramp at the IRAMP pin, producing a linear di/dt of current to the load.