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参数资料
| 型号： | TPS2393APWRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO14 |
| 封装： | GREEN, PLASTIC, TSSOP-14 |
| 文件页数： | 7/30页 |
| 文件大小： | 665K |
| 代理商： | TPS2393APWRG4 |
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TPS2393A
SLUS610 JULY 2004
15
www.ti.com
DETAILED DESCRIPTION
Current fault response timing and retry duty cycle are accomplished by the fault timer block in conjunction with
an external capacitor connected between the FLTTIME and VIN pins. Whenever the hot swap controller is in
current control mode, such as during inrush limiting at insertion, or in response to excessive demand during
operation of the plug-in, the LCA asserts the OVERCURRENT signal shown in Figure 24. This signal starts the
charging of the FLTTIME capacitor. If this capacitor charges to the pin’s 4-V trip threshold, the fault is latched.
A latched fault disables the LCA drive, and turns on a large pull-down device at the GATE output to rapidly turn
off the external FET. The fault condition is indicated by turning on the open-drain FAULT output driver. A latched
fault also causes discharge of the external capacitor at the IRAMP pin, in order to reset the hot swap circuit for
the next output enable event. Slow discharge of the timing capacitor at about 1/100th the charging rate initiates
fault retry operation at a 1% duty cycle. This enables periodic testing for persistance or removal of the fault
condition.
An internal overload comparator (OLC in Figure 24) also monitors the ISENS voltage against a nominal 100-mV
threshold. This comparator provides circuit breaker protection against sudden current fault conditions, such as
a load short-circuit. The OVERLOAD output of this comparator also drives the fault timer. In this case, the timer
circuit applies only a 4-
s deglitch filter to help reduce nuisance trips. However, if the overload condition exceeds
the filter length, the FET is momentarily snapped off, after which it is quickly turned back on in current ramp or
current limit mode. At this point, fault timing commences as above.
The PG pin is an open-drain, active-low indication of a load power good status. Load voltage sensing is provided
at the DRAINSNS pin. To assert PG, the device must not be in latched current fault status, the DRAINSNS pin
must be pulled below the 1.35-V nominal threshold, and the voltage at the IRAMP pin must be greater than
approximately 5 V. This last criteria ensures that maximum allowed sourcing current is available to the load
before declaring power good. Once all the conditions are met, the PG status is latched on-chip. This prevents
instances of momentary current-limit operation (e.g., due to load surges or voltage spikes on the input supply)
from propagating through to the PG output. However, if input conditions are not met, or if a persistent load fault
does result in fault timeout, the PG latch will be cleared.
Additional details of the ramp generator operation are shown in Figure 25. To enable the generator, the large
NMOS device shown in this circuit is turned off. This allows a small current source to charge the external
capacitor connected at the IRAMP pin. The voltage ramp on the capacitor actually has two discrete, linear
slopes. As shown in Figure 25, current is supplied from either of two sources. An internal comparator monitors
the IRAMP voltage level, and selects the appropriate charging rate. Initially at turn-on, when the pin voltage is
0 V, the 600-nA source is selected, to provide a slow turn-on (or reduced-rate) sourcing period. This slow turn-on
ensures that the LCA is pulled out of saturation, and is slewing to the voltage at its non-inverting input before
normal rate load charging is allowed. This scheme helps reduce or eliminate current steps at the external FET
on-threshold. Once the voltage at the IRAMP pin reaches approximately 0.5 V, the SLOW signal is deasserted,
and the 10-
A source is selected for the remainder of the ramp period.
The IRAMP pin voltage is divided down by a factor of 100, and applied to the non-inverting input of the LCA (see
Figure 24). Although the IRAMP capacitor is charged to about 6.5 V, the VLIM reference is clamped at 40 mV.
Therefore, current sourced to the load during turn-on is limited to a value given by IMAX
≤ 40 mV/RSENSE, where
RSENSE is the value of the external sense resistor. Therefore, both load current maximum slew rate and peak
magnitude are easily set with just two external components.
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相关代理商/技术参数 |
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| TPS2393DBT | 功能描述:热插拔功率分布 Full Featured -48V Industral Temp. RoHS:否 制造商:Texas Instruments 产品:Controllers & Switches 电流限制: 电源电压-最大:7 V 电源电压-最小:- 0.3 V 工作温度范围: 功率耗散: 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Tube |
| TPS2393DBTG4 | 功能描述:热插拔功率分布 Full Featured -48V Industral Temp. RoHS:否 制造商:Texas Instruments 产品:Controllers & Switches 电流限制: 电源电压-最大:7 V 电源电压-最小:- 0.3 V 工作温度范围: 功率耗散: 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Tube |
| TPS2393DBTR | 功能描述:热插拔功率分布 Full Featured -48V Industral Temp. RoHS:否 制造商:Texas Instruments 产品:Controllers & Switches 电流限制: 电源电压-最大:7 V 电源电压-最小:- 0.3 V 工作温度范围: 功率耗散: 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Tube |
| TPS2393DBTRG4 | 功能描述:热插拔功率分布 -48V Hot Swap G179 Pwr Mgr Ind Temp RoHS:否 制造商:Texas Instruments 产品:Controllers & Switches 电流限制: 电源电压-最大:7 V 电源电压-最小:- 0.3 V 工作温度范围: 功率耗散: 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Tube |
| TPS2393EVM | 功能描述:电源管理IC开发工具 Simple -48V Hot Swap Contr EVM RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
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