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| 型号： | TPS40054PWPRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封装： | GREEN, PLASTIC, HTSSOP-16 |
| 文件页数： | 14/35页 |
| 文件大小： | 866K |
| 代理商： | TPS40054PWPRG4 |
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f
SW +
T
J*TA
qJA VDD
* IQ
2
Qg
(Hz)
(43)
LAYOUT CONSIDERATIONS
MOSFET PACKAGING
GROUNDING AND CIRCUIT LAYOUT CONSIDERATIONS
www.ti.com ...................................................................................................................................... SLUS593F – DECEMBER 2003 – REVISED SEPTEMBER 2008
MOSFET package selection depends on MOSFET power dissipation and the projected operating conditions. In
general, for a surface-mount applications, the DPAK style package provides the lowest thermal impedance (
θ
JA)
and, therefore, the highest power dissipation capability. However, the effectiveness of the DPAK depends on
proper layout and thermal management. The
θ
JA specified in the MOSFET data sheet refers to a given copper
area and thickness. In most cases, a lowest thermal impedance of 40°C/W requires one square inch of 2-ounce
copper on a G-10/FR-4 board. Lower thermal impedances can be achieved at the expense of board area. Please
refer to the selected MOSFET's data sheet for more information regarding proper mounting.
The TPS4005x provides separate signal ground (SGND) and power ground (PGND) pins. It is important that
circuit grounds are properly separated. Each ground should consist of a plane to minimize its impedance if
possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling
capacitor (BP10), and the input capacitor should be connected to PGND plane at the input capacitor.
Sensitive nodes such as the FB resistor divider, RT, and ILIM should be connected to the SGND plane. The
SGND plane should only make a single point connection to the PGND plane.
Component placement should ensure that bypass capacitors (BP10 and BP5) are located as close as possible to
their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located
near high dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW).
Copyright 2003–2008, Texas Instruments Incorporated
21
Product Folder Link(s): TPS40054 TPS40055 TPS40057
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