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SLVS795C – OCTOBER 2008 – REVISED OCTOBER 2010
Once the slow start time is known, the slow start capacitor value can be calculated using
Equation 6. For the
example circuit, the slow start time is not too critical since the output capacitor value is 47mF which does not
require much current to charge to 3.3V. The example circuit has the slow start time set to an arbitrary value of
1ms which requires a 3.3 nF capacitor.
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Bootstrap Capacitor Selection
A 0.1-mF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10V
or higher voltage rating.
Under Voltage Lock Out Set Point
The Under Voltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54160. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 7.25V (enabled). After the regulator starts switching, it should
continue to do so until the input voltage falls below 6.25V (UVLO stop).
The programmable UVLO and enable voltages are set using a resistor divider between Vin and ground to the EN
pin.
Equation 2 through
Equation 3 can be used to calculate the resistance values necessary. For the example
application, a 332k
between Vin and EN and a 61.9k between EN and ground are required to produce the
7.25 and 6.25 volt start and stop voltages.
Output Voltage and Feedback Resistors Selection
For the example design, 10.0 k
was selected for R2. Using
Equation 1, R1 is calculated as 31.25 k. The
nearest standard 1% resistor is 31.6 k
. Due to current leakage of the VSENSE pin, the current flowing through
the feedback network should be greater than 1 mA in order to maintain the output voltage accuracy. This
requirement makes the maximum value of R2 equal to 800 k
. Choosing higher resistor values will decrease
quiescent current and improve efficiency at low output currents but may introduce noise immunity problems.
Compensation
There are several industry techniques used to compensate DC/DC regulators. The method presented here yields
high phase margins. For most conditions, the regulator will have a phase margin between 60 and 90 degrees.
The method presented here ignores the effects of the slope compensation that is internal to the TPS54160.
Since the slope compensation is ignored, the actual crossover frequency is usually lower than the crossover
frequency used in the calculations.
Use SwitcherPro software for a more accurate design.
The uncompensated regulator will have a dominant pole, typically located between 300 Hz and 3 kHz, due to the
output capacitor and load resistance and a pole due to the error amplifier. One zero exists due to the output
capacitor and the ESR. The zero frequency is higher than either of the two poles.
If left uncompensated, the double pole created by the error amplifier and the modulator would lead to an unstable
regulator. To stabilize the regulator, one pole must be canceled out. One design approach is to locate a
compensating zero at the modulator pole. Then select a crossover frequency that is higher than the modulator
pole. The gain of the error amplifier can be calculated to achieve the desired crossover frequency. The capacitor
used to create the compensation zero along with the output impedance of the error amplifier form a low
frequency pole to provide a minus one slope through the crossover frequency. Then a compensating pole is
added to cancel the zero due to the output capacitors ESR. If the ESR zero resides at a frequency higher than
the switching frequency then it can be ignored.
Copyright 2008–2010, Texas Instruments Incorporated
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