(
)
(
) (
)
Omax
IN min
O max
DS(on) max
D
O max
L
D
V
= 0.91 ×
V
I
× R
+ V
I
× R
V
-
(
)
(
)
(
)
Omin
IN max
Omin
D
O min
L
D
V
= 0.051
V
I
Rin
+ V
I
R
V
-
-
-
SLUS859B
– OCTOBER 2008 – REVISED FEBRUARY 2011
C7 = 220 pF
The measured overall loop response for the circuit is given in
Figure 12. Note that the actual closed loop
crossover frequency is higher than intended at about 25 kHz. This is primarily due to variation in the actual
values of the output filter components and tolerance variation of the internal feed-forward gain circuitry. Overall
the design has greater than 60 degrees of phase margin and will be completely stable over all combinations of
line and load variability.
BOOTSTRAP CAPACITOR
Every TPS54233 design requires a bootstrap capacitor, C4. The bootstrap capacitor must be 0.1
μF. The
bootstrap capacitor is located between the PH pins and BOOT pin. The bootstrap capacitor should be a
high-quality ceramic type with X7R or X5R grade dielectric for temperature stability.
CATCH DIODE
The TPS54233 is designed to operate using an external catch diode between PH and GND. The selected diode
must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum
voltage at the PH pin, which is VINMAX + 0.5 V. Peak current must be greater than IOUTMAX plus on half the peak
to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note that
the catch diode conduction time is typically longer than the high-side FET on time, so attention paid to diode
parameters can make a marked improvement in overall efficiency. Additionally, check that the device chosen is
capable of dissipating the power losses. For this design, a Diodes, Inc. B340A is chosen, with a reverse voltage
of 40 V, forward current of 3 A, and a forward voltage drop of 0.5 V.
OUTPUT VOLTAGE LIMITATIONS
Due to the internal design of the TPS54233, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 91%
(31)
Where:
VIN min = Minimum input voltage
IO max = Maximum load current
VD = Catch diode forward voltage
RL = Output inductor series resistance
The equation assumes maximum on resistance for the internal high-side FET.
The lower limit is constrained by the minimum controllable on time which may be as high as 160 ns. The
approximate minimum output voltage for a given input voltage and minimum load current is given by
Equation 32:(32)
Where:
VIN max = Maximum input voltage
IO min = Minimum load current
VD = Catch diode forward voltage
RL = Output inductor series resistance
This equation assumes nominal on-resistance for the high-side FET and accounts for worst case variation of
operating frequency set point. Any design operating near the operational limits of the device should be carefully
checked to assure proper functionality.
POWER DISSIPATION ESTIMATE
The following formulas show how to estimate the device power dissipation under continuous conduction mode
operations. They should not be used if the device is working in the discontinuous conduction mode (DCM) or
pulse skipping Eco-modeTM.
16
2008–2011, Texas Instruments Incorporated