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参数资料
型号： TPS54972PWP
厂商： TEXAS INSTRUMENTS INC
元件分类： 稳压器
英文描述： 16 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28
封装： GREEN, PLASTIC, HTSSOP-28
文件页数： 13/19页
文件大小： 411K
代理商： TPS54972PWP
TPS54972
www.ti.com
SLVS437B – AUGUST 2002 – REVISED AUGUST 2010
DISSIPATION RATINGS
(1) (2)
THERMAL IMPEDANCE
TA = 25°C
TA = 70°C
TA = 85°C
PACKAGE
JUNCTION-TO-AMBIENT
POWER RATING
28 Pin PWP with solder
14.4°C/W
6.94 W(3)
3.81 W
2.77 W
28 Pin PWP without solder
27.9°C/W
3.58 W
1.97 W
1.43 W
(1)
For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
(2)
Test board conditions:
(a) 3 inch x 3 inch, 4 layers, thickness: 0.062 inch
(b) 1.5 oz. copper traces located on the top of the PCB
(c) 1.5 oz. copper ground plane on the bottom of the PCB
(d) 12 thermal vias (See Recommended Land Pattern in applications section of this data sheet)
(3)
Maximum power dissipation may be limited by overcurrent protection.
ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VI = 3 V to 4 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE, VIN
VIN
Input voltage range
3.0
4.0
V
fs = 350 kHz, RT open, PH pin open
11
15.8
I(Q)
Quiescent current
fs = 500 kHz, RT = 100 k, PH pin open
16
23.5
mA
Shutdown, SS/ENA = 0 V
1
1.4
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
2.95
3.0
V
Stop threshold voltage, UVLO
2.7
2.8
V
Hysteresis voltage, UVLO
0.14
0.16
V
Rising and falling edge deglitch, UVLO(1)
2.5
s
BIAS VOLTAGE
Output voltage, VBIAS
I(VBIAS) = 0
2.70
2.80
2.90
V
Output current, VBIAS (2)
100
mA
REGULATION
Line regulation(1) (3)
IL = 4 A, fs = 350 kHz, TJ = 85°C
0.04
%/V
Load regulation(1) (3)
IL = 0 A to 8 A, fs = 350 kHz, TJ = 85°C
0.03
%/A
OSCILLATOR
Internally set free running frequency
RT open
280
350
420
kHz
RT = 180 k
(1% resistor to AGND)
252
280
308
Externally set free running frequency range
RT = 100 k
(1% resistor to AGND)
460
500
540
kHz
RT = 68 k
(1% resistor to AGND)
663
700
762
Ramp valley(1)
0.75
V
Ramp amplitude (peak-to-peak)(1)
1
V
Minimum controllable on time(1)
200
ns
Maximum duty cycle(1)
90%
ERROR AMPLIFIER
Error amplifier open loop voltage gain
1 k
COMP to AGND(1)
90
110
dB
Error amplifier unity gain bandwidth
Parallel 10 k
, 160 pF COMP to AGND(1)
3
5
MHz
Error amplifier common mode input voltage
Powered by internal LDO(1)
0
VBIAS
V
range
Input bias current, VSENSE
VSENSE = Vref
60
250
nA
Output voltage slew rate (symmetric), COMP
1.0
1.4
V/ms
(1)
Specified by design
(2)
Static resistive loads only
(3)
Specified by the circuit used in Figure 8
Copyright 2002–2010, Texas Instruments Incorporated
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