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参数资料
| 型号： | TPS54972PWP |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 16 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封装： | GREEN, PLASTIC, HTSSOP-28 |
| 文件页数： | 6/19页 |
| 文件大小： | 411K |
| 代理商： | TPS54972PWP |
TPS54972
SLVS437B – AUGUST 2002 – REVISED AUGUST 2010
www.ti.com
ERROR AMPLIFIER
The high performance, wide bandwidth, voltage error amplifier sets the TPS54972 apart from most dc/dc
converters. The user has a wide range of output L and C filter components to suit the particular application
needs. Type 2 or type 3 compensation can be employed using external compensation components.
PWM CONTROL
Signals from the error amplifier output, oscillator and current limit circuit are processed by the PWM control logic.
Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch.
Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse
width. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to
charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the
error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and
turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM
ramp.
During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM latch is never reset and the high-side FET remains on
until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The
device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting
VSENSE to approximately the same voltage as VREF. If the error amplifier output is low, the PWM latch is
continually reset, and the high-side FET does not turn on. The low-side FET remains on until the VSENSE
voltage decreases to a range that allows the PWM comparator to change states. The TPS54972 is capable of
sinking current continuously until the output reaches the regulation set-point.
If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds
the error amplifier output. The high-side FET turns off, and the low-side FET turns on to decrease the energy in
the output inductor and consequently the output current. This process is repeated each cycle in which the current
limit comparator is tripped.
DEAD-TIME CONTROL AND MOSFET DRIVERS
Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side
driver does not turn on until the gate drive voltage to the low-side FET is below 2 V, while the low-side driver
does not turn on until the voltage at the gate of the high-side MOSFET is below 2 V. The high-side and low-side
drivers are designed with 300-mA source and sink capability to quickly drive the power MOSFETs gates. The
low-side driver is supplied from VIN, while the high-side drive is supplied from the BOOT pin. A bootstrap circuit
uses an external BOOT capacitor and an internal 2.5-
. bootstrap switch connected between the VIN and BOOT
pins. The integrated bootstrap switch improves drive efficiency and reduces external component count.
OVERCURRENT PROTECTION
The cycle by cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and
comparing this signal to a preset overcurrent threshold. The high side MOSFET is turned off within 200 ns of
reaching the current limit threshold. A 100 ns leading edge blanking circuit prevents false tripping of the current
limit when the high-side switch is turning on. Current limit detection occurs only when current flows from VIN to
PH when sourcing current to the output filter. Load protection during current sink operation is provided by thermal
shutdown.
THERMAL SHUTDOWN
The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from shutdown automatically when the junction temperature
decreases to 10°C below the thermal shutdown trip point, and starts up under control of the slow-start circuit.
Thermal shutdown provides protection when an overload condition is sustained for several milliseconds. With a
persistent fault condition, the device cycles continuously; starting up by control of the soft-start circuit, heating up
due to the fault condition, and then shutting down upon reaching the thermal limit trip point. This sequence
repeats until the fault condition is removed.
14
Copyright 2002–2010, Texas Instruments Incorporated
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