参数资料
型号: TPS54972PWP
厂商: TEXAS INSTRUMENTS INC
元件分类: 稳压器
英文描述: 16 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28
封装: GREEN, PLASTIC, HTSSOP-28
文件页数: 19/19页
文件大小: 411K
代理商: TPS54972PWP
VIN
C4
10 F
R2
10 k
C2
470 pF
C1
12 pF
R 3
301
R1
10 k
C3
470 pF
C12
1 F
C11
22 F
C9
22 F
C7
22 F
VTTQ
L1
0.65 H
C5
3300 pF
R4
2.4
U1
TPS54972PWP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AGND
VSENSE
COMP
STATUS
BOOT
PH
RT
ENA
REFIN
VBIAS
VIN
PGND
C6
0.047 F
PwrPad
C8
10 F
C10
1 F
R 5
71.5 k
R 7
10 k
R 6
10 k
C14
0.1 F
C13
0.1 F
VDDQ
TPS54972
www.ti.com
SLVS437B – AUGUST 2002 – REVISED AUGUST 2010
Figure 8. Application Circuit
OUTPUT FILTER
The output filter is composed of a 0.65-mH inductor and three 22-mF capacitors. The inductor is a low dc
resistance (0.017
) type, Pulse PA0277 0.65-mH. The capacitors used are 22 mF, 6.3-V ceramic types with X5R
dielectric. An additional 1-mF output capacitor (C12) is included to suppress high frequencies.
PCB LAYOUT
Figure 9 shows a generalized PCB layout guide for the TPS54972.
The VIN pins should be connected together on the printed circuit board (PCB) and bypassed with a low ESR
ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor
connections, the VIN pins, and the TPS54X10 ground pins. The minimum recommended bypass capacitance is
10 mF ceramic with a X5R or X7R dielectric and the optimum placement is closest to the VIN pins and the PGND
pins.
The TPS54972 has two internal grounds (analog and power). Inside the TPS54972, the analog ground ties to all
of the noise sensitive signals, while the power ground ties to the noisier power signals. Noise injected between
the two grounds can degrade the performance of the TPS54972, particularly at higher output currents. However,
ground noise on an analog ground plane can also cause problems with some of the control and bias signals. For
these reasons, separate analog and power ground traces are recommended. There should be an area of ground
one the top layer directly under the IC, with an exposed area for connection to the PowerPAD. Use vias to
connect this ground area to any internal ground planes. Use additional vias at the ground side of the input and
output filter capacitors as well. The AGND and PGND pins should be tied to the PCB ground by connecting them
to the ground area under the device as shown. The only components that should tie directly to the power ground
plane are the input capacitors, the output capacitors, the input voltage decoupling capacitor, and the PGND pins
of the TPS54972. Use a separate wide trace for the analog ground signal path. This analog ground should be
used for the voltage set point divider, timing resistor RT and bias capacitor grounds. Connect this trace directly to
AGND (Pin 1).
The PH pins should be tied together and routed to the output inductor. Since the PH connection is the switching
node, inductor should be located very close to the PH pins and the area of the PCB conductor minimized to
prevent excessive capacitive coupling.
Copyright 2002–2010, Texas Instruments Incorporated
9
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