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| 型号： | TPS62410DRCR |
| 厂商： | Texas Instruments |
| 文件页数： | 3/33页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 0.8A 10SON |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 0.6 V ~ 6 V |
| 输入电压： | 2.5 V ~ 6 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 2.25MHz |
| 电流 - 输出： | 800mA |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-VFDFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 10-SON 裸露焊盘（3x3） |
| 产品目录页面： | 1033 (CN2011-ZH PDF) |
| 其它名称： | 296-25488-6 |
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www.ti.com
SLVS737 – FEBRUARY 2007
ELECTRICAL CHARACTERISTICS
V IN = 3.6V, V OUT = 1.8V, EN = V IN , MODE = GND, L = 2.2 μ H, C OUT = 20 μ F, T A = –40 ° C to 85 ° C typical values are at T A =
25 ° C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
V IN
Input voltage range
One converter, I OUT = 0mA. PFM mode enabled
2.5
19
6.0
29
V
μ A
(Mode = 0) device not switching,
EN1 = 1 OR EN2 = 1
I Q
Operating quiescent current
Two converter, I OUT = 0mA. PFM mode enabled
(Mode = 0) device not switching,
EN1 = 1 AND EN2 = 1
I OUT = 0mA, MODE/DATA = GND, for one
converter, V OUT 1.575V (1)
I OUT = 0mA, MODE/DATA = V IN , for one
converter, V OUT 1.575V (1)
32
23
3.6
48
μ A
μ A
mA
I SD
V UVLO
Shutdown current
Undervoltage lockout threshold
EN1, EN2 = GND, V IN = 3.6V (2)
EN1, EN2 = GND, V IN ramped from 0V to 3.6V (3)
Falling
Rising
1.2
0.1
1.5
3
1
2.35
2.4
μ A
V
ENABLE EN1, EN2
V IH
V IL
High-level input voltage, EN1, EN2
Low-level input voltage, EN1, EN2
1.2
0
V IN
0.4
V
V
I IN
Input bias current, EN1, EN2
EN1, EN2 = GND or VIN
0.05
1.0
μ A
DEF_1 INPUT
I IN
Input biasd current DEF_1
DEF_1 = GND or VIN
0.01
1.0
μ A
MODE/DATA
V IH
High-level input voltage,
1.2
V IN
V
MODE/DATA
V IL
Low-level input voltage,
0
0.4
V
MODE/DATA
I IN
V OH
V OL
Input bias current, MODE/DATA
Acknowledge output voltage high
Acknowledge output voltage low
MODE/DATA = GND or VIN
Open drain, via external pullup resistor
Open drain, sink current 500 μ A
0
0.01
1.0
V IN
0.4
μ A
V
V
INTERFACE TIMING
t Start
Start time
2
μ s
t H_LB
t L_LB
High time low bit, logic 0 detection
Low time low bit, logic 0 detection
Signal level on MODE/DATA pin is > 1.2V
Signal level on MODE/DATA pin < 0.4V
2
2x
200
400
μ s
μ s
t H_LB
t L_HB
t H_LB
Low time high bit, logic 1 detection
High time high bit, logic 1 detection
Signal level on MODE/DATA pin < 0.4V
Signal level on MODE/DATA pin is > 1.2V
2
2x
200
400
μ s
μ s
t L_HS
T EOS
End of Stream
T EOS
2
μ s
t ACKN
Duration of acknowledge condition
V IN 2.5V to 6V
400
520
μ s
(MODE/DATE line pulled low by the
device)
t valACK
Acknowledge valid time
2
μ s
t timeout
Timeout for entering power save
MODE/DATA Pin changes from high to low
520
μ s
mode
(1)
(2)
(3)
Device is switching with no load on the output, L = 3.3 μ H, value includes losses of the coil
These values are valid after the device has been already enabled one time (EN1 or EN2 = high) and supply voltage V IN has not
powered down.
These values are valid when the device is disabled (EN1 and EN2 low) and supply voltage V IN is powered up. The values remain valid
until the device has been enabled first time (EN1 or EN2 = high). After first enable, Note 3 becomes valid.
3
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