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POWER SAVE MODE OPERATION
I
=
PFMDCDC1 enter
I
=
PFMDCDC2 enter
I
=
PFMDCDC3 enter
VINDCDC1
VINDCDC2
VINDCDC3
24 W
26 W
39 W
(1)
I
=
PFMDCDC1 leave
I
=
PFMDCDC2 leave
I
=
PFMDCDC3 leave
VINDCDC1
VINDCDC2
VINDCDC3
18 W
20 W
29 W
(2)
SLVS607B – SEPTEMBER 2005 – REVISED JULY 2007
DETAILED DESCRIPTION (continued)
The step-down converter outputs (when enabled) are monitored by power good (PG) comparators, the outputs
of which are available via the serial interface. The outputs of the dc-dc converters can be optionally discharged
via on-chip 300
resistors when the dc-dc converters are disabled. This feature can be enabled using the I2C
interface.
During PWM operation, the converters use a unique fast response voltage mode controller scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on. The inductor current ramps up until the comparator trips and the control logic turns off the switch. The
current limit comparator also turns off the switch if the current limit of the P-channel switch is exceeded. After the
adaptive dead time used to prevent shoot through current, the N-channel MOSFET rectifier is turned on, and the
inductor current ramps down. The next cycle is initiated by the clock signal, again turning off the N-channel
rectifier and turning on the P-channel switch.
The three dc-dc converters operate synchronized to each other with the VDCDC1 converter as the master. A
180
°° phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90° shift to the VDCDC3
switch turn on decreases the input RMS current and smaller input capacitors can be used. This is optimized for
a typical application where the VDCDC1 converter regulates a Li-Ion battery voltage of 3.7 V to 3.3 V, the
VDCDC2 converter from 3.7 V to 2.5 V, and the VDCDC3 converter from 3.7 V to 1.5 V. The phase of the three
converters can be changed using the CON_CTRL register.
As the load current decreases, the converters enter the power save mode operation. During PSM, the
converters operate in a burst mode (PFM mode) with a frequency between 750 kHz and 1.5 MHz, nominal for
one burst cycle. However, the frequency between different burst cycles depends on the actual load current and
is typically far less than the switching frequency with a minimum quiescent current to maintain high efficiency.
In order to optimize the converter efficiency at light load, the average current is monitored and if in PWM mode
the inductor current remains below a certain threshold, then PSM is entered. The typical threshold to enter PSM
is calculated as follows:
During the PSM the output voltage is monitored with a comparator, and by maximum skip burst width. As the
output voltage falls below the threshold, set to the nominal VO, the P-channel switch turns on and the converter
effectively delivers a constant current defined as follows.
22