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| 型号： | TPS65020RHAR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQCC40 |
| 封装： | GREEN, PLASTIC, QFN-40 |
| 文件页数： | 18/48页 |
| 文件大小： | 1182K |
| 代理商： | TPS65020RHAR |
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SYSTEM RESET + CONTROL SIGNALS
PB_IN and PB_OUT
Interrupt Management and the INT Pin
SLVS607B – SEPTEMBER 2005 – REVISED JULY 2007
DETAILED DESCRIPTION (continued)
Table 2. Control Pins and Status Outputs for DC-DC Converters
PIN NAME
INPUT
FUNCTION
OUTPUT
Defines the default voltage of the VDCDC3 switching converter. DEFDCDC3 = 0 defaults VDCDC3 to
DEFDCDC3
I
1.3 V, DEFDCDC3 = VCC defaults VDCDC3 to 1.55 V.
Defines the default voltage of the VDCDC2 switching converter. DEFDCDC2 = 0 defaults VDCDC2 to
DEFDCDC2
I
1.8 V, DEFDCDC2 = VCC defaults VDCDC2 to 2.5 V.
Defines the default voltage of the VDCDC1 switching converter. DEFDCDC1 = 0 defaults VDCDC1 to 3 V,
DEFDCDC1
I
DEFDCDC1 = VCC defaults VDCDC1 to 3.3 V.
DCDC3_EN
I
Set DCDC3_EN = 0 to disable and DCDC3_EN = 1 to enable the VDCDC3 converter
DCDC2_EN
I
Set DCDC2_EN = 0 to disable and DCDC2_EN = 1 to enable the VDCDC2 converter
DCDC1_EN
I
Set DCDC1_EN = 0 to disable and DCDC1_EN = 1 to enable the VDCDC1 converter
The HOT_RESET pin generates a reset (RESPWRON) for the processor.HOT_RESET does not alter any
TPS65020 settings except the output voltage of VDCDC3. Activating HOT_RESET sets the voltage of
HOT_RESET
I
VDCDC3 to its default value defined with the DEFDCDC3 pin. A 1 M
pull-up resistor to VCC is integrated
in TPS65020. HOT_RESET is internally de-bounced by the TPS65020.
RESPWRON is held low when power is initially applied to the TPS65020. The VRTC voltage is monitored:
RESPWRON
O
RESWPRON is low when VRTC < 2.4 V and remains low for a time defined by the external capacitor at
the TRESPWRON pin. RESPWRON can also be forced low by activation of the HOT_RESET pin.
TRESPWRON
I
Connect a capacitor here to define the RESET time at the RESPWRON pin. 1 nF typically gives 100 ms.
The RESPWRON signal can be used as a global reset for the application. It is an open drain output. The
RESPWRON signal is generated according to the power good comparator of VRTC, and remains low for
tnrespwron seconds after VRTC has risen above 2.52 V (falling threshold is 2.4 V, 5% hysteresis). tnrespwron is set by
an external capacitor at the TRESPWRON pin. 1 nF gives typically 100 ms. RESPWRON is also triggered by
the HOT_RESET input. This input is internally debounced, with a filter time of typically 30 ms.
The PWRFAIL and LOW_BAT signals are generated by two voltage detectors using the PWRFAIL_SNS and
LOWBAT_SNS input signals. Each input signal is compared to a 1 V threshold (falling edge) with 5% (50 mV)
hysteresis.
The VDCDC3 converter is reset to its default output voltage defined by the DEFDCDC3 input, when
HOT_RESET is asserted. Other I2C registers are not affected. Generally, the VDCDC3 converter is set to its
default voltage with one of these conditions: HOT_RESET active, VRTC lower than its threshold voltage,
undervoltage lockout (UVLO) condition, RESPWRON active, both VDCDC3-converter AND VDCDC1-converter
disabled. In addition, the voltage of VDCDC3 changes to 1xxx0, if the VDCDC1 converter is disabled. Where xxx
is the state before VDCDC1 was disabled.
In the TPS65020 the PB_IN pin is defined as an input. It is active high and debounces the input signal. For
example from a push button, before passing it to a latch associated with PB_OUT (active low). This feature
allows the implementation of a push-button on-off-switch. PB_OUT is actively pulled low per default. See the
application information section.
The INT pin combines the outputs of the PGOOD comparators from each dc-dc converter and LDOs. The INT
pin is used as a POWER_OK pin indicating when all enabled supplies are in regulation. If the PGOODZ register
is read via the serial interface, any active bits are then blocked from the INT output pin.
Interrupts can be masked using the MASK register; default operation is not to mask any DCDC or LDO
interrupts since this provides the POWER_OK function.
25
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