参数资料
型号: TPS65020RHAR
厂商: TEXAS INSTRUMENTS INC
元件分类: 电源管理
英文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQCC40
封装: GREEN, PLASTIC, QFN-40
文件页数: 21/48页
文件大小: 1182K
代理商: TPS65020RHAR
www.ti.com
t
DEGLITCH
t
DEGLITCH
t
DEGLITCH
PB_IN
(GPIO1)
PB_OUT
(GPIO2)
ON-OFF
VCC
PWRFAIL
ThresholdDependingonExternalVoltageDividerConnectedtoVCC
0.8V
SERIAL INTERFACE
DataLine
Stable;
DataValid
DATA
CLK
Change
ofData
Allowed
SLVS607B – SEPTEMBER 2005 – REVISED JULY 2007
Figure 29. PB-ON-OFF Timing
The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to
400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed
to new values depending on the instantaneous application requirements and charger status to be monitored.
Register contents remain intact as long as VCC remains above 2 V. The TPS65020 has a 7bit address:
1001000, other addresses are available upon contact with the factory. Attempting to read data from the register
addresses not listed in this section results in FFh being read out.
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a
start condition and terminated with a stop condition. When addressed, the TPS65020 device generates an
acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TPS65020 device must pull down the DATA line
during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock
pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end
of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In
this case, the slave TPS65020 device must leave the data line high to enable the master to generate the stop
condition
Figure 30. Bit Transfer on the Serial Interface
28
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