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参数资料
| 型号： | TPS65020RHAR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQCC40 |
| 封装： | GREEN, PLASTIC, QFN-40 |
| 文件页数： | 48/48页 |
| 文件大小： | 1182K |
| 代理商： | TPS65020RHAR |
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ELECTRICAL CHARACTERISTICS
SLVS607B – SEPTEMBER 2005 – REVISED JULY 2007
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VLDO1 and VLDO2 LOW DROPOUT REGULATORS
VI
Input voltage range for LDO1, 2
1.5
6.5
V
VO
LDO1 output voltage range
1
3.3
V
VO
LDO2 output voltage range
1
3.3
V
Maximum output current for LDO1,
IO
200
mA
LDO2
LDO1 and LDO2 short-circuit
I(SC)
VLDO1 = GND, VLDO2 = GND
400
mA
current limit
IO = 50 mA, VINLDO = 1.8 V
120
Minimum voltage drop at LDO1,
IO = 50 mA, VINLDO = 1.5 V
65
150
mV
LDO2
IO = 200 mA, VINLDO = 1.8 V
300
Output voltage accuracy for LDO1,
IO = 10 mA
–2%
1%
LDO2
VINLDO1,2 = VLDO1, 2 + 0.5 V
Line regulation for LDO1, LDO2
–1%
1%
(min. 2.5 V) to 6.5 V, IO = 10 mA
Load regulation for LDO1, LDO2
IO = 0 mA to 50 mA
–1%
1%
Regulation time for LDO1, LDO2
Load change from 10% to 90%
10
μs
ANALOGIC SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3
VIH
High level input voltage
1.3
VCC
V
VIL
Low level input voltage
0
0.1
V
IH
Input bias current
0.001
0.05
μA
LOGIC SIGNALS PB_IN; PB_OUT
VOL
Low level output voltage at PB_OUT
IOL = 20 mA
0.5
V
VOH
High level output voltage PB_OUT
6
V
VIL
Low level input voltage PB_IN
0.4
V
VIH
High level input voltage PB_IN
1.3
VCC
(1)
V
II Input leakage current PB_IN
1
μA
THERMAL SHUTDOWN
T(SD)
Thermal shutdown
Increasing junction temperature
160
°C
Thermal shutdown hysteresis
Decreasing junction temperature
20
°C
INTERNAL UNDERVOLTAGE LOCK OUT
UVLO
Internal UVLO
VCC falling
–2%
2.35
2%
V
V(UVLO_HYST)
Internal UVLO comparator hysteresis
120
mV
VOLTAGE DETECTOR COMPARATORS
Comparator threshold
Falling threshold
–1%
1.0
1%
V
(PWRFAIL_SNS, LOWBAT_SNS)
Hysteresis
40
50
60
mV
Propagation delay
25 mV overdrive
10
μs
POWER GOOD
VDCDC1, VDCDC2, VDCDC3, VLDO1,
V(PGOODF)
–12%
–10%
–8%
VLDO2, decreasing
VDCDC1, VDCDC2, VDCDC3, VLDO1,
V(PGOODR)
–7%
–5%
–3%
VLDO2, increasing
(1)
The input voltage can go as high as 6 V. If the input voltage exceeds VCC, an input current of (V(PB_IN) - 0.7 V - VCC) / 10 k flows.
9
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