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参数资料
| 型号： | TSC87C51-33CBB |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 33 MHz, MICROCONTROLLER, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 60/80页 |
| 文件大小： | 5152K |
| 代理商： | TSC87C51-33CBB |
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260
XMEGA A [MANUAL]
8077I–AVR–11/2012
23.5.2 STATUS
– AES Status register
Bit 7
– ERROR: Error
The ERROR flag indicates an illegal handling of the AES crypto module. The flag is set in the following cases:
Setting START in the control register while the state memory and/or key memory are not fully loaded or read. This
error occurs when the total number of read/write operations from/to the STATE and KEY registers is not a multiple
of 16 before an AES start.
Accessing (read or write) the control register while the START bit is one.
This flag can be cleared by software by writing one to its bit location.
Bit 6:1
– Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
Bit 0
– SRIF: State Ready Interrupt flag
This flag is the interrupt/DMA request flag, and is set when the encryption/decryption procedure is completed and the
state memory contains valid data. As long as the flag is zero, this indicates that there is no valid encrypted/decrypted
data in the state memory.
The flag is cleared by hardware when a read access is made to the state memory (the first byte is read). Alternatively, the
bit can be cleared by writing a one to its bit location.
23.5.3 STATE
– AES State register
The STATE register is used to access the state memory. Before encryption/decryption can take place, the state memory
must be written sequentially, byte-by-byte, through the STATE register. After encryption/decryption is done, the
ciphertext/plaintext can be read sequentially, byte-by-byte, through the STATE register.
Loading the initial data to the STATE register should be done after setting the appropriate AES mode and direction. This
register can not be accessed during encryption/decryption.
23.5.4 KEY
– Key register
The KEY register is used to access the key memory. Before encryption/decryption can take place, the key memory must
be written sequentially, byte-by-byte, through the KEY register. After encryption/decryption is done, the last subkey can
be read sequentially, byte-by-byte, through the KEY register. Loading the initial data to the KEY register should be done
after setting the appropriate AES mode and direction.
Bit
765
432
10
+0x01
ERROR
–
–SRIF
Read/Write
R/W
R
R/W
Initial Value
000
00
Bit
765
43
210
+0x02
STATE[7:0]
Read/Write
R/W
Initial Value
000
00
000
Bit
7654
3210
+0x03
KEY[7:0]
Read/Write
R/W
Initial Value
0
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