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| 型号： | TSC87C51-33CBB |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 33 MHz, MICROCONTROLLER, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 7/80页 |
| 文件大小： | 5152K |
| 代理商： | TSC87C51-33CBB |
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199
2466T–AVR–07/10
ATmega16(L)
Combining Several
TWI Modes
In some cases, several TWI modes must be combined in order to complete the desired action.
Consider for example reading data from a serial EEPROM. Typically, such a transfer involves
the following steps:
1.
The transfer must be initiated
2.
The EEPROM must be instructed what location should be read
3.
The reading must be performed
4.
The transfer must be finished
Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct
the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data
must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must
be changed. The Master must keep control of the bus during all these steps, and the steps
should be carried out as an atomical operation. If this principle is violated in a multi-master sys-
tem, another Master can alter the data pointer in the EEPROM between steps 2 and 3, and the
Master will read the wrong data location. Such a change in transfer direction is accomplished by
transmitting a REPEATED START between the transmission of the address byte and reception
of the data. After a REPEATED START, the Master keeps ownership of the bus. The following
figure shows the flow in this transfer.
Figure 94. Combining Several TWI Modes to Access a Serial EEPROM
Multi-master
Systems and
Arbitration
If multiple Masters are connected to the same bus, transmissions may be initiated simultane-
ously by one or more of them. The TWI standard ensures that such situations are handled in
such a way that one of the Masters will be allowed to proceed with the transfer, and that no data
will be lost in the process. An example of an arbitration situation is depicted below, where two
Masters are trying to transmit data to a Slave Receiver.
Figure 95. An Arbitration Example
Master Transmitter
Master Receiver
S = START
Rs = REPEATED START
P = STOP
Transmitted from Master to Slave
Transmitted from Slave to Master
S
SLA+W
A
ADDRESS
A
Rs
SLA+R
A
DATA
A
P
Device 1
MASTER
TRANSMITTER
Device 2
MASTER
TRANSMITTER
Device 3
SLAVE
RECEIVER
Device n
SDA
SCL
........
R1
R2
V
CC
相关PDF资料 |
PDF描述 |
|---|---|
| TSC87C52-33CDB | 8-BIT, OTPROM, 33 MHz, MICROCONTROLLER, PQFP44 |
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| TSC87251A1XXX-B16IDB | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP44 |
| TSC51C1XXX-A16CD | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDSO44 |
| TSC80C31-L16CYD | 8-BIT, 16 MHz, MICROCONTROLLER, UUC40 |
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