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参数资料
| 型号： | TSC87C51-33CBB |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 33 MHz, MICROCONTROLLER, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 64/80页 |
| 文件大小： | 5152K |
| 代理商： | TSC87C51-33CBB |
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264
XMEGA A [MANUAL]
8077I–AVR–11/2012
Figure 24-1. Base Address
24.3.2 Address Size
The address size selects how many bits of the address should be compared when generating a chip select. The address
size can be anywhere from 256 bytes to 16MB. If the address space is set to anything larger than 4KB, the base address
must be on a boundary equal to the address space. For example, with 1MB address space for a chip select, the base
address must be on a 1MB, 2MB, etc. boundary.
If the EBI is configured so that the address spaces overlap, the internal memory space will have priority, followed by chip
select 0 (CS0), CS1, CS2, and CS3.
24.3.3 Chip Select as Address Lines
If any chip select lines are unused, these can, in some combinations, be used as address lines. This enables larger
external memory or external CS generation. Each column in Figure 24-2 on page 264 shows enabled chip select lines
(CSn) and the address lines available on unused chip select lines (An). The right-hand column shows that all four CS
lines are used as address lines when only CS3 is enabled.
Figure 24-2. Chip Select and address line combinations
24.4
EBI Clock
The EBI is clocked from the Peripheral 2x (ClkPER2) Clock. This clock can run at the CPU Clock frequency, or at two times
the CPU Clock frequency. This can be used to lower the EBI access time. Refer to “System Clock and Clock Options” on
page 79 for details the Peripheral 2x Clock and how to configure this.
24.5
SRAM Configuration
When used with SRAM, the EBI can be configured with no multiplexing, or it can employ various address multiplexing
modes by using external address latches. When a limited number of pins are available on the device for the EBI, address
latch enable (ALE) signals are used to control the external latches that multiplex address lines from the EBI. The
ADDRESS[23:n]
BASEADDR[23:n]
=
ADDRESS[n-1:0]
A[n-1:0]
D[7:0]
CS
CS3
CS2
CS1
CS0
CS3
CS2
CS1
A16
CS3
CS2
A17
A16
A19
A18
A17
A16
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