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| 型号： | TSC87C52-20IAD |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PDIP40 |
| 封装： | PLASTIC, DIP-40 |
| 文件页数： | 17/46页 |
| 文件大小： | 4720K |
| 代理商： | TSC87C52-20IAD |
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23
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
7.
Power Management and Sleep Modes
The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low
power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, thereby
saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the
application’s requirements.
7.1
Sleep Modes
Figure 6-1 on page 17 presents the different clock systems and their distribution in ATtiny20. The figure is helpful in
selecting an appropriate sleep mode. Table 7-1 shows the different sleep modes and their wake up sources.
Table 7-1.
Active Clock Domains and Wake-up Sources in Different Sleep Modes
Notes: 1. For INT0, only level interrupt.
2. Only TWI address match interrupt.
To enter any of the four sleep modes, the SE bits in MCUCR must be written to logic one and a SLEEP instruction must
be executed. The SM[2:0] bits in the MCUCR register select which sleep mode (Idle, ADC Noise Reduction, Standby or
Power-down) will be activated by the SLEEP instruction. See Table 7-2 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four
cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction
following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a
reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
Note that if a level triggered interrupt is used for wake-up the changed level must be held for some time to wake up the
MCU (and for the MCU to enter the interrupt service routine). See “External Interrupts” on page 37 for details.
7.1.1
Idle Mode
When bits SM[2:0] are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but
allowing the analog comparator, ADC, timer/counters, watchdog, TWI, SPI and the interrupt system to continue
operating. This sleep mode basically halts clkCPU and clkNVM, while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the timer overflow.
If wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting
the ACD bit in “ACSRA – Analog Comparator Control and Status Register” on page 106. This will reduce power
consumption in idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.
Sleep Mode
Active Clock Domains
Oscillators
Wake-up Sources
clk
CPU
clk
NVM
clk
IO
clk
ADC
Main
Clock
Source
Enabled
INT0
and
Pin
Change
W
atchdog
Interrupt
TWI
Slave
ADC
Other
I/O
Idle
X
ADC Noise Reduction
X
X
X(2)
X
Standby
X
X
X(2)
Power-down
X
X(2)
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