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参数资料
| 型号： | TSC87C52-20IAD |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PDIP40 |
| 封装： | PLASTIC, DIP-40 |
| 文件页数： | 44/46页 |
| 文件大小： | 4720K |
| 代理商： | TSC87C52-20IAD |
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97
42023G–SAM–03/2014
ATSAM4L8/L4/L2
instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the
external pins during normal operation of the part.
When using the JTAG interface for Boundary-Scan, the JTAG TCK clock is independent of the
internal chip clock, which is not required to run.
NOTE: For pins connected to 5V lines care should be taken to not drive the pins to a logic one
using boundary scan, as this will create a current flowing from the 3,3V driver to the 5V pullup on
the line. Optionally a series resistor can be added between the line and the pin to reduce the
current.
8.11.7
Flash Programming Typical Procedure
Flash programming is performed by operating Flash controller commands. The Flash controller
is connected to the system bus matrix and is then controllable from the AHP-AP. The AHB-AP
cannot write the FLASH page buffer while the core_hold_reset is asserted. The AHB-AP cannot
be accessed when the device is in protected state. It is important to ensure that the CPU is
halted prior to operating any flash programming operation to prevent it from corrupting the sys-
tem configuration. The recommended sequence is shown below:
1.
At power up, RESET_N is driven low by a debugger. The on-chip regulator holds the
system in a POR state until the input supply is above the POR threshold. The system
continues to be held in this static state until the internally regulated supplies have
reached a safe operating.
2.
PM starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash
Clock, and any Bus Clocks that do not have clock gate control). Internal resets are
maintained due to the external reset.
– The Debug Port (DP) and Access Ports (AP) receives a clock and leave the reset
state,
3.
The debugger maintains a low level on TCK and release RESET_N.
– The SMAP asserts the core_hold_reset signal
4.
The Cortex-M4 core remains in reset state, meanwhile the rest of the system is
released.
5.
The debugger then configures the NVIC to catch the Cortex-M4 core reset vector fetch.
For more information on how to program the NVIC, refer to the ARMv7-M Architecture
Reference Manual.
6.
The debugger writes a one in the SMAP SCR.HCR to release the Cortex-M4 core reset
to make the system bus matrix accessible from the AHB-AP.
7.
The Cortex-M4 core initializes the SP, then read the exception vector and stalls
8.
Programming is available through the AHB-AP
9.
After operation is completed, the chip can be restarted either by asserting RESET_N or
switching power off/on or clearing SCR.HCR. Make sure that the TCK pin is high when
releasing RESET_N not to halt the core.
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