- 您现在的位置：买卖IC网 > PDF目录300044 > TSPC603PVG6LE (ATMEL CORP) 32-BIT, 166 MHz, RISC PROCESSOR, CBGA255 PDF资料下载
参数资料
| 型号： | TSPC603PVG6LE |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 166 MHz, RISC PROCESSOR, CBGA255 |
| 封装： | 21 MM, 3.16 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件页数： | 8/38页 |
| 文件大小： | 599K |
| 代理商： | TSPC603PVG6LE |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页
TSPC603P
16/38
D Sleep mode sequence :
- Set sleep bit (HID0[10] = 1).
- 603p asserts quiesce request (QREQ).
- System asserts quiesce acknowledge (QACK).
- 603p enters sleep mode after several processor clocks.
D Several methods of returning to full-power mode :
- Assert INT, SMI, or MCP interrupts.
- Assert hard reset or soft reset.
D PLL may be disabled and SYSCLK may be removed while in sleep mode.
D Return to full-power mode after PLL and SYSCLK disabled in sleep mode :
- Enable SYSCLK.
- Reconfigure PLL into desired processor clock mode.
- System logic waits for PLL startup and relock time (100
msec).
- System logic asserts one of the sleep recovery signals (for example, INT or SMI).
3.6.4. Power Management Software Considerations
Since the 603p is a dual issue processor with out -of-order execution capability, care must be taken in how the power management
mode is entered. Furthermore, nap and sleep modes require all outstanding bus operations to be completed before the power man-
agement mode is entered. Normally during system configuration time, one of the power management modes would be selected by
setting the appropriate HID0 mode bit. Later on, the power management mode is invoked by setting the MSR[POW] bit. To provide a
clean transition into and out of the power management mode, the stmsr[POW] should be preceded by a sync instruction and fol-
lowed by an isync instruction.
3.6.5. Power dissipation
Table 8 : Power dissipation
Vdd/AVdd = 2.5
± 5 % V dc, OVdd = 3.3 ± 5 % V dc, GND = 0 V dc, 0°C ≤ Tc ≤ 125°C
CPU clock Frequency
166 MHz
200 MHz
Units
Full-On Mode (DPM Enabled)
Typical
3.0
4.0
W
Max
4.0
5.0
W
Doze Mode(1)
Typical
1.2
1.5
W
Nap Mode(1)
Typical
80
120
mW
Sleep Mode(1)
Typical
70
100
mW
Sleep Mode-PLL Disabled(1)
Typical
60
mW
Sleep Mode-PLL and SYSCLK Disabled(1)
Typical
60
mW
(1) The values provided for this mode do not include pad driver power (OVDD) or
analog supply power (AVDD). Worst-case AVDD = 15 mW
Notes:
1. To calculate the power consumption at low temperature (–55 oC), use a 1.25 factor
2. Maximum power measurements are performed with a worst case instruction mix at VDD=2.625 V
3. These values apply for all valid PLL settings and do not include OVDD/AVDD consumption
4. WORST case AVDD = 15 mW, OVDD is system dependent but is typically
≤ 10 % VDD
相关PDF资料 |
PDF描述 |
|---|---|
| TSPDF11FGSRA0 | PUSHBUTTON SWITCH, SPDT, MOMENTARY, 0.02A, 20VDC, SURFACE MOUNT-RIGHT ANGLE |
| TSS21NGRA | SLIDE SWITCH, DPDT, LATCHED, 0.02A, 20VDC, THROUGH HOLE-RIGHT ANGLE |
| TSS901ESASL3 | 3 CHANNEL(S), 200M bps, SERIAL COMM CONTROLLER, QFP196 |
| TSSH-106-01-L-D | 12 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SOLDER |
| TSSH-108-01-T-DV | 16 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSPC603R | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RCAB/Q8L | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RCAB/Q8LC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8L | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8LC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
发布紧急采购，3分钟左右您将得到回复。