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参数资料
| 型号： | TSPC860SRMZPU50D4 |
| 厂商： | E2V TECHNOLOGIES PLC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 50 MHz, RISC PROCESSOR, PBGA357 |
| 封装： | PLASTIC, BGA-357 |
| 文件页数： | 30/90页 |
| 文件大小： | 2351K |
| 代理商： | TSPC860SRMZPU50D4 |
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36
TSPC860
2129A–HIREL–08/02
B13a
CLKOUT to TA, BI High Z (when driven by the
Memory Controller or PCMCIA interface)
2.50
15
2.50
15
2.50
15
2.50
15
ns
B14
CLKOUT to TEA assertion
2.50
10
2.50
10
2.50
10
2.50
9
ns
B15
CLKOUT to TEA High Z
2.50
152.50
15
2.50152.5015
ns
B16
TA, BI valid to CLKOUT (Setup Time)
9.75
–
9.75
–
9.75
–
6
–
ns
B16a
TEA, KR, RETRY, CR valid to CLKOUT
(Setup Time)
10–10–10
–
4.50
–
ns
B16b
BB, BG, BR, valid to CLKOUT (setup time)
8.50
–
8.50
–
8.50
–
4
–
ns
B17
CLKOUT to TA, TEA, BI, BB, BG, BR valid
(Hold Time)
1–
1–1
–
2
–
ns
B17a
CLKOUT to KR, RETRY, CR valid (Hold Time)
2
–
2
–
2
–
2
–
ns
B18
D(0:31), DP(0:3) valid to CLKOUT Rising Edge
(Setup Time)
6–
6–6
–
6
–
ns
B19
CLKOUT Rising Edge to D(0:31), DP(0:3) valid
(Hold Time)
1–
1–1
–
2
–
ns
B20
D(0:31), DP(0:3) valid to CLKOUT Falling Edge
(Setup Time)
4–
4–4
–
4
–
ns
B21
CLKOUT Falling Edge to D(0:31), DP(0:3) valid
(Hold Time)
2–
2–2
–
2
–
ns
B22
CLKOUT Rising Edge to CS asserted
-GPCM- ACS = 00
7.58
14.33
6.25
13
5
11.75
3.80
10.04
ns
B22a
CLKOUT Falling Edge to CS asserted
-GPCM- ACS = 11, TRLX = 0, EBDF = 0
–8
–8–
8
–
8
ns
B22b
CLKOUT Falling Edge to CS asserted
-GPCM- ACS = 11, TRLX = 0, EBDF = 0
7.58
14.33
6.25
13
5
11.75
3.80
10.54
ns
B22c
CLKOUT Falling Edge to CS asserted
-GPCM- ACS = 11, TRLX = 0, EBDF = 1
10.86
17.99
8.88
16
7
14.13
5.18
12.31
ns
B23
CLKOUT Rising Edge to CS negated
-GPCM- Read Access,
-GPCM- write access, ACS = ‘00’, TRLX = ‘0’ &
CSNT = ‘0’
28
282
8
2
ns
B24
A(0:31) and BADDR(28:30) to CS asserted
-GPCM- ACS = 10, TRLX = 0
5.58
–
4.25
–
3
–
1.79
–
ns
B24a
A(0:31) and BADDR(28:30) to CS asserted
-GPCM- ACS = 11, TRLX = 0
13.15
–
10.5
–
8
–
5.58
–
ns
B25
CLKOUT Rising Edge to OE,WE(0:3) asserted
–
9
–
9
–
9
–
9
ns
B26
CLKOUT Rising Edge to OE negated
2
9
2
9
2
9
2
9
ns
B27
A(0:31) and BADDR(28:30) to CS asserted
-GPCM- ACS = 10, TRLX = 1
35.88
–
29.25
–
23
–
16.94
–
ns
B27a
A(0:31) and BADDR(28:30) to CS asserted
-GPCM- ACS = 11, TRLX = 1
43.45
–
35.50
–
28
–
20.73
–
ns
Table 8. Bus Operation Timings (Continued)
Num
Characteristic
33 MHz
40 MHz
50 MHz
66 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
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