参数资料
型号: TSS463-AA
英文描述: TSS463-AA [Updated 3/03. 60 Pages]
中文描述: TSS463 -机管局[更新3月3日。 60页]
文件页数: 23/52页
文件大小: 268K
代理商: TSS463-AA
TSS461C
23
Rev. D (22 Feb 01)
9.2.2. Transmit Control Register (0x01) :
7
6
5
4
3
2
1
0
MR3
MR2
MR1
MR0
VER2
VER1
VER0
MT
Read/Write register.
Default value after reset : 0x02
MR[3:0]
: Maximum Retries.
These bits allow the user to control the amount of retries the circuit will
perform if any errors occurred during transmission.
Table 4. Retries
MR [3:0]
Max. Nb of retry
Max. Nb of transmis
0000
0
1
0001
1
2
0010
2
3
0011
3
4
0100
4
5
0101
5
6
0110
6
7
0111
7
8
1000
8
9
1001
9
10
1010
10
11
1011
11
12
1100
12
13
1101
13
14
1110
14
15
1111
15
16
Note : Bus contention is not regarded as an error and that an infinite
number of transmission attempts will be performed
if bus contention
occurs continuously.
VER[2:0]:
DLC Version after reset.
000 : TSS461A & B
001 : TSS461C
These bits must not be set by user; 001 must always be written to these
bits.
MT:
Module type
The three different module types are supported (see section 7.2.):
One: The TSS461C is at once an autonomous module (Rank 0), an
synchronous access module (Rank 1) or a slave module (Rank 16).
Zero: The TSS461C is at once an synchronous access module
(Rank 1) or a slave module (Rank 16).
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