TSS461C
5
Rev. D (22 Feb 01)
5.1.1. INTEL Mode
The INTEL mode interface consists of 13 pins. 8 pins are the multiplexed address and data bus, and the rest are the
address strobe, the read and write commands, the chip select and the interrupt request pins.
To access the memory locations in INTEL mode, the processor must first assert a valid address on the multiplexed
address and data bus and drive the address strobe pin high. When the required set-up time has passed the processor must
drive the address strobe low, and keep the address valid for the required hold time.
The processor must then either assert the data to be written on the address and data bus, if a write is intended, or float
the data bus for a read. The next step is to drive either the write or read command pins low, according to the function
required, and at the same time drive the chip select pin high.
The TSS461C access cycle is then terminated by driving the chip select and command pins low.
Note, that the chip select pin may be driven high for the entire access cycle, and may also remain high during and after
the termination of the cycle.
ALE
AD[7:0]
RD
WR
CS
ADDRESS
DATA TO BE
WRITTEN
ADDRESS
DATA
READ
WRITE CYCLE
READ CYCLE
Figure 4. INTEL Read and Write Cycles.
5.1.2. MOTOROLA Mode
In MOTOROLA mode the WR pin becomes the R/W command, the RD pin must be connected to ground and the CS
pin becomes the E strobe. This means that there is no separate chip select input, i.e. if some external decoder is to be
used, this decoder should not drive the E input high unless the processors E output is high as well.
Please refer to Figure 5. for the MOTOROLA read and write cycles. The main difference between INTEL and
MOTOROLA mode is that the timing in INTEL mode is referenced to the command signals (RD and WR), but in
MOTOROLA mode the reference is the E signal.
ALE
AD[7:0]
VSS (RD)
R/W (WR)
E (CS)
ADDRESS
DATA TO BE
WRITTEN
ADDRESS
DATA
READ
WRITE CYCLE
READ CYCLE
Figure 5. MOTOROLA Read and Write Cycles.