TSS461C
32
Rev. D (22 Feb 01)
Table 4: Channel Register Set Structure
Reg. Name
Offset
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ID_MASK
0x07
ID_M [3:0]
x
x
x
x
ID_MASK
0x06
ID_M [11:4]
(no register)
0x05
x
x
x
x
x
x
x
x
(no register)
0x04
x
x
x
x
x
x
x
x
MESS_L / STA
0x03
M_L [4:0]
CHER
CHTx
CHRx
MESS_PTR
0x02
DRACK
M_P [6:0]
ID_TAG / CMD
0x01
ID_T [3: 0]
EXT
RAK
RNW
RTR
ID_TAG
0x00
ID_T [11:4]
9.3.1. Identifier Tag and Command Registers:
The identifier tag and command registers is located at the base_address and base_address + 1. It allows the user to
specify the full 12-bit identifier field of the ISO standard and the 4-bit command.
7
6
5
4
3
2
1
0
ID_T 3
ID_T 2
ID_T 1
ID_T 0
EXT
RAK
RNW
RTR
base_address
+ 0x01
7
6
5
4
3
2
1
0
ID_T 11
ID_T 10
ID_T 9
ID_T 8
ID_T 7
ID_T 6
ID_T 5
ID_T 4
base_address
+ 0x00
Read / Write registers.
ID_T [11:0]
: Identifier Tag
Upon a reception hit (i.e, a good comparison between the identifier
received and an identifier specified, taking the comparison mask into
account, as well as a status and command indicating a message to be
received), the identifier tag bits value will be rewritten with the identifier
bits actually received.
EXT, RAK, RNW & RTR:
(See section 11.)
No comparison will be done on the command bits, excepted on EXT bit.
The RAK, RNW and RTR bits will be written into the first byte of the
Message upon a reception hit.
The RNW and RTR bits, as well as the status bits in the length and status
register, must be in a valid position for reception or transmission. If not,
the message corresponding to this identifier is considered as inactive or
invalid.
The way of knowing if an acknowledge sequence was requested or not
is to check the first byte of the Message.