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参数资料
| 型号： | TVP5150AZQCR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 颜色信号转换 |
| 英文描述： | COLOR SIGNAL DECODER, PBGA48 |
| 封装： | PLASTIC, BGA-48 |
| 文件页数： | 11/74页 |
| 文件大小： | 439K |
| 代理商： | TVP5150AZQCR |
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29
2.15 I2C Host Interface
The I2C standard consists of two signals, serial input/output data line (SDA) and input/output clock line (SCL), which
carry information between the devices connected to the bus. A third signal (I2CSEL) is used for slave address
selection. Although the I2C system can be multimastered, the TVP5150A decoder functions as a slave device only.
Both SDA and SCL must be connected to a positive supply voltage via a pullup resistor. When the bus is free, both
lines are high. The slave address select terminal (I2CSEL) enables the use of two TVP5150A decoders tied to the
same I2C bus. At power up, the status of the I2CSEL is polled. Depending on the write and read addresses to be used
for the TVP5150A decoder, it can either be pulled low or high through a resistor. This terminal is multiplexed with
YOUT7 and hence must not be tied directly to ground or VDD. Table 26 summarizes the terminal functions of the
I2C-mode host interface.
Table 25. Write Address Selection
I2CSEL
WRITE ADDRESS
0
B8h
1
BAh
Table 26. I2C Terminal Description
SIGNAL
TYPE
DESCRIPTION
I2CSEL (YOUT7)
I
Slave address selection
SCL
I/O (open drain)
Input/output clock line
SDA
I/O (open drain)
Input/output data line
Data transfer rate on the bus is up to 400 kbits/s. The number of interfaces connected to the bus is dependent on
the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the high period of the SCL except
for start and stop conditions. The high or low state of the data line can only change with the clock signal on the SCL
line being low. A high-to-low transition on the SDA line while the SCL is high indicates an I2C start condition. A
low-to-high transition on the SDA line while the SCL is high indicates an I2C stop condition.
Every byte placed on the SDA must be 8 bits long. The number of bytes which can be transferred is unrestricted. Each
byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by the I2C master.
2.15.1 I2C Write Operation
Data transfers occur utilizing the following illustrated formats.
An I2C master initiates a write operation to the TVP5150A decoder by generating a start condition (S) followed by
the TVP5150A I2C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle. After
receiving an acknowledge from the TVP5150A decoder, the master presents the subaddress of the register, or the
first of a block of registers it wants to write, followed by one or more bytes of data, MSB first. The TVP5150A decoder
acknowledges each byte after completion of each transfer. The I2C master terminates the write operation by
generating a stop condition (P).
Step 1
0
I2C Start (master)
S
Step 2
7
6
5
4
3
2
1
0
I2C General address (master)
1
0
1
0
X
0
Step 3
9
I2C Acknowledge (slave)
A
Step 4
7
6
5
4
3
2
1
0
I2C Write register address (master)
addr
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| TVP5150PBSG4 | 功能描述:视频 IC VERY LOW POWER VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作电源电压:5 V 电源电流:80 mA 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-28 封装:Reel |
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| TVP5150PBSRG4 | 制造商:Texas Instruments 功能描述: |
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