Detailed Description
11
SLES043 — September 2002
TVP5150
2.5.5 Timing Processor
The timing processor is a combination of hardware and software running in the microprocessor that serves
to control horizontal lock to the input sync pulse edge, AGC, offset adjustment in the analog front end, vertical
sync detection, and Macrovision
detection.
The sync input is filtered by a FIR filter for noise reduction. Coarse lock detects the falling or rising edge of
the filtered sync input by comparing pixels against a threshold. The coarse phase error is read by the
microprocessor and used to make coarse adjustments to the horizontal DTO frequency. After coarse lock has
moved the sync edge within the fine lock window, the fine lock is enabled to make fine adjustments to the
horizontal DTO frequency such that the edge is centered within the window to sub pixel accuracy.
The gain and offset of the AFE is adjusted such that the sync height and back porch levels achieve target
values. Filtered samples of the sync tip and back porch are read and processed by the microprocessor. The
gain that is applied to the sync input is also applied to the chroma input. Filtered samples of the chroma
blanking level are read and processed by the microprocessor to adjust the chroma offset to set the blanking
level to the midpoint of the ADC range.
The vertical sync is detected at the input by comparing half line accumulated pixel values against an adaptive
threshold. Sequential patterns of half line-accumulated results are used to detect odd and even field syncs.
The presence of Macrovision is detected by the presence of pseudosyncs by coarse lock. A counter tracks
the number of edges detected after the horizontal sync edge has been detected.
2.5.6 VBI Data Processor
The TVP5150 vertical blank interval (VBI) data processor (VDP) slices various data services like Teletext
(WST, NABST), closed caption (CC), wide screen signaling (WSS) etc. These services are acquired by
programming the VDP to enable a standard(s) in the VBI. The results are stored in a FIFO and/or registers.
The Teletext results are stored in a FIFO only. Table 2–1 gives a summary of the types of VBI data supported
according to the video standard. It supports both square pixel and ITU-R BT. 601 sampling for each standard.
The 26 standard modes are currently supported. Nevertheless, the TVP5150 VDP can be used for custom
modes. TI may provide the RAM content of custom modes when the customer asks with a full custom VBI spec.
One configuration for a standard consists of 15 bytes of data. However, addressing of the RAM has steps of
16 bytes for a convenience.
Table 2–1. Data Types Supported by the VDP
LINE MODE REGISTER
(D0h–FBh) Bit[3:0]
SAMPLING RATE
(0Dh) Bit 7
NAME
DESCRIPTION
0000b
X
Reserved
0000b
X
Reserved
0001b
0
WST PAL B S
Teletext, PAL, system B, square
0001b
1
WST PAL B 6
Teletext, PAL, system B, ITU-R BT 601
0010b
0
WST PAL C S
Teletext, PAL, system C, square
0010b
1
WST PAL C 6
Teletext, PAL, system C, ITU-R BT 601
0011b
0
WST, NTSC B S
Teletext, NTSC, system B, square
0011b
1
WST, NTSC B 6
Teletext, NTSC, system B, ITU-R BT 601
0100b
0
NABTS, NTSC C S
Teletext, NTSC, system C, square
0100b
1
NABTS, NTSC C 6
Teletext, NTSC, system C, ITU-R BT 601
0101b
0
TTX, NTSC D S
Teletext, NTSC, system D (Japan), square
0101b
1
TTX, NTSC D 6
Teletext, NTSC, system D (Japan), ITU-R BT 601
0110b
0
CC, PAL S
Closed caption PAL square
0110b
1
CC, PAL 6
Closed caption PAL ITU-R BT 601
0111b
0
CC. NTSC S
Closed caption NTSC, square
0111b
1
CC, NTSC 6
Closed caption NTSC, ITU-R BT 601