参数资料
型号: UPD44647186AF5-E22-FQ1
厂商: Renesas Electronics America
文件页数: 13/42页
文件大小: 0K
描述: SRAM QDRII 72MBIT 165-PBGA
标准包装: 1
格式 - 存储器: RAM
存储器类型: SRAM - 同步,QDR II+
存储容量: 72M(4M x 18)
速度: 450MHz
接口: 并联
电源电压: 1.7 V ~ 1.9 V
工作温度: 0°C ~ 70°C
封装/外壳: 165-LBGA
供应商设备封装: 165-PBGA(13x15)
包装: 散装
μ PD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Truth Table
2.0 Clock Cycles Read Latency
[ μ PD44647094A-A], [ μ PD44647184A-A], [ μ PD44647364A-A]
WRITE cycle
Operation
CLK
L → H
R#
H
W#
L
Data in
D or Q
Load address, input write data on two
consecutive K and K# rising edge
READ cycle
Load address, read data on two
consecutive K and K# rising edge
NOP (No operation)
Clock stop
L → H
L → H
Stopped
L
H
X
X
H
X
Input data
Input clock
Data out
Output data
Output clock
D = X, Q = High-Z
Previous state
D A (A+0)
K(t+1) ↑
Q A (A+0)
K(t+2) ↑
D A (A+1)
K#(t+1) ↑
Q A (A+1)
K#(t+2) ↑
D A (A+2)
K(t+2) ↑
Q A (A+2)
K(t+3) ↑
D A (A+3)
K#(t+2) ↑
Q A (A+3)
K#(t+3) ↑
2.5 Clock Cycles Read Latency
[ μ PD44647096A-A], [ μ PD44647186A-A], [ μ PD44647366A-A]
WRITE cycle
Operation
CLK
L → H
R#
H
W#
L
Data in
D or Q
Load address, input write data on two
consecutive K and K# rising edge
READ cycle
Load address, read data on two
consecutive K and K# rising edge
NOP (No operation)
Clock stop
L → H
L → H
Stopped
L
H
X
X
H
X
Input data
Input clock
Data out
Output data
Output clock
D = X, Q = High-Z
Previous state
D A (A+0)
K(t+1) ↑
Q A (A+0)
K#(t+2) ↑
D A (A+1)
K#(t+1) ↑
Q A (A+1)
K(t+3) ↑
D A (A+2)
K(t+2) ↑
Q A (A+2)
K#(t+3) ↑
D A (A+3)
K#(t+2) ↑
Q A (A+3)
K(t+4) ↑
Remarks
Remarks listed below are for both products with 2.0 and 2.5 Clock Cycles Read Latency.
1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at K and K# rising edges.
3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
K. All control inputs are registered during the rising edge of K.
4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = K# when clock is stopped. This is not essential but permits most rapid restart
by overcoming transmission line charging symmetrically.
7. If R# was LOW to initiate the previous cycle, this signal becomes a don't care for this WRITE operation
however it is strongly recommended that this signal is brought HIGH as shown in the truth table.
8. W# during write cycle and R# during read cycle were HIGH on previous K clock rising edge. Initiating
consecutive READ or WRITE operations on consecutive K clock rising edges is not permitted. The
device will ignore the second request.
Data Sheet M19962EJ2V0DS
11
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