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参数资料
| 型号： | UPD44647186AF5-E22-FQ1 |
| 厂商： | Renesas Electronics America |
| 文件页数： | 9/42页 |
| 文件大小： | 0K |
| 描述： | SRAM QDRII 72MBIT 165-PBGA |
| 标准包装： | 1 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 同步，QDR II+ |
| 存储容量： | 72M（4M x 18） |
| 速度： | 450MHz |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.9 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 165-LBGA |
| 供应商设备封装： | 165-PBGA（13x15） |
| 包装： | 散装 |
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μ PD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Pin Identification
Symbol
A
D0 to Dxx
Q0 to Qxx
R#
W#
BWx#
K, K#
CQ, CQ#
ZQ
DLL#
QVLD
ODT
TMS
TDI
TCK
TDO
V REF
V DD
V DD Q
V SS
NC
Type
Input
Input
Output
Input
Input
Input
Input
Output
Input
Input
Output
Input
Input
Input
Output
–
Supply
Supply
Supply
–
Description
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. All transactions operate on a burst of four words (two clock periods of bus
activity). These inputs are ignored when device is deselected, i.e., NOP (R# = W# = HIGH).
Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K
and K# during WRITE operations. See Pin Configurations for ball site location of individual signals.
x9 device uses D0 to D8.
x18 device uses D0 to D17.
x36 device uses D0 to D35.
Synchronous Data Outputs: Output data is synchronized to the respective K and K# rising edges.
Data is output in synchronization with K and K#, depending on the R# command. See Pin
Configurations for ball site location of individual signals.
x9 device uses Q0 to Q8.
x18 device uses Q0 to Q17.
x36 device uses Q0 to Q35.
Synchronous Read: When LOW this input causes the address inputs to be registered and a READ
cycle to be initiated. This input must meet setup and hold times around the rising edge of K. If a READ
command (R# = LOW) is input, an input of R# on the subsequent rising edge of K is ignored.
Synchronous Write: When LOW this input causes the address inputs to be registered and a WRITE
cycle to be initiated. This input must meet setup and hold times around the rising edge of K. If a
WRITE command (W# = LOW) is input, an input of W# on the subsequent rising edge of K is ignored.
Synchronous Byte Writes: When LOW these inputs cause their respective byte to be registered and
written during WRITE cycles. These signals must meet setup and hold times around the rising edges
of K and K# for each of the two rising edges comprising the WRITE cycle. See Pin Configurations
for signal to data relationships.
x9 device uses BW0#.
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
See Byte Write Operation for relation between BWx# and Dxx.
Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of
phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges.
Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the
synchronous data outputs and can be used as a data valid indication. These signals run freely and do
not stop when Q tristates. If K and K# are stopped, CQ and CQ# will also stop.
Output Impedance Matching Input: This input is used to tune the device outputs to the system data
bus impedance. Q, CQ, CQ# and QVLD output impedance are set to 0.2 x RQ, where RQ is a resistor
from this bump to ground. The output impedance can be minimized by directly connect ZQ to V DD Q.
This pin cannot be connected directly to GND or left unconnected. The output impedance is adjusted
every 20 μ s upon power-up to account for drifts in supply voltage and temperature. After replacement
for a resistor, the new output impedance is reset by implementing power-on sequence.
DLL/PLL Disable: When DLL# is LOW, the operation can be performed at a clock frequency slower
than TKHKH (MAX.) without the DLL/PLL circuit being used. The AC/DC characteristics cannot be
guaranteed. For normal operation, DLL# must be HIGH and it can be connected to V DD Q through a 10
k Ω or less resistor.
Q valid Output: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ#.
ODT Control Input: When the ODT control pin is HIGH, the ODT function is turned on at Dxx and
BWx# pins. The ODT resistors are set to 0.6 x RQ, where RQ is a resistor from ZQ pin bump to
ground. When the ODT Control pin is LOW or No Connect, the ODT function is turned off. The ODT
ON/OFF is set at power-on sequence. The ODT can not change the state after power-on. To enable
ODT function, ODT pin must be HIGH and it can be connected to V DD Q through a 10 k Ω or less
resistor.
IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the JTAG function
is not used in the circuit.
IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to V SS if the JTAG function is not used
in the circuit.
IEEE 1149.1 Test Output: 1.8 V I/O level.
When providing any external voltage to TDO signal, it is recommended to pull up to V DD .
HSTL Input Reference Voltage: Nominally V DD Q/2. Provides a reference voltage for the input buffers.
Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC
Characteristics for range.
Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible. See
Recommended DC Operating Conditions and DC Characteristics for range.
Power Supply: Ground
No Connect: These signals are not connected internally.
Data Sheet M19962EJ2V0DS
7
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| UPD44647186AF5-E22-FQ1-A | 功能描述:SRAM QDRII 72MBIT 165-PBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
| UPD44647186AF5-E25-FQ1 | 功能描述:SRAM QDRII 72MBIT 165-PBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
| UPD44647186AF5-E25-FQ1-A | 功能描述:SRAM QDRII 72MBIT 165-PBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
| UPD44647366AF5-E22-FQ1 | 功能描述:SRAM QDRII 72MBIT 165-PBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
| UPD44647366AF5-E22-FQ1-A | 功能描述:SRAM QDRII 72MBIT 165-PBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
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