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CHAPTER 19 INTERRUPT FUNCTIONS
User’s Manual U17260EJ6V0UD
502
Table 19-2. Flags Corresponding to Interrupt Request Sources (2/2)
Interrupt Request Flag
Interrupt Mask Flag
Priority Specification Flag
Interrupt
Source
Register
INTAD
ADIF
IF1L
ADMK
MK1L
ADPR
PR1L
INTSR0
SRIF0
SRMK0
SRPR0
INTWTI
WTIIF
WTIMK
WTIPR
INTTM51
Note 1
TMIF51
TMMK51
TMPR51
INTKR
KRIF
KRMK
KRPR
INTWT
WTIF
WTMK
WTPR
INTP6
PIF6
PMK6
PPR6
INTP7
PIF7
PMK7
PPR7
INTIIC0
Note 2
IICIF0
Note 4
IICMK0
Note 5
IICPR0
Note 6
INTDMU
Note 2, 3
DMUIF
Note 3, 4
IF1H
DMUMK
Note 3, 5
MK1H
DMUPR
Note 3, 6
PR1H
INTCSI11
Note 3
CSIIF11
Note 3
CSIMK11
Note 3
CSIPR11
Note 3
INTTM001
Note 3
TMIF001
Note 3
TMMK001
Note 3
TMPR001
Note 3
INTTM011
Note 3
TMIF011
Note 3
TMMK011
Note 3
TMPR011
Note 3
Notes 1.
When 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated upon
the timing when the INTTM5H1 signal is generated (see Figure 9-13 Transfer Timing).
2.
Do not use serial interface IIC0 and multiplier/divider simultaneously, because the flags corresponding to
the interrupt request sources of serial interface IIC0 and multiplier/divider support both of these interrupt
request sources. If software which operates serial interface IIC0 is developed by CC78K0 which is C
compiler, do not select the check box of “Using Multiplier/Divider” on GUI of PM+.
3.
PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D only.
4.
If either interrupt source INTIIC0 or INTDMU is generated, bit 0 of IF1H is set (1).
5.
Bit 0 of MK1H supports both interrupt sources INTIIC0 and INTDMU.
6.
Bit 0 of PR1H supports both interrupt sources INTIIC0 and INTDMU.
(1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or
upon reset signal generation.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt
routine is entered.
IF0L, IF0H, IF1L, and IF1H are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H, and
IF1L and IF1H are combined to form 16-bit registers IF0 and IF1, they are set by a 16-bit memory manipulation
instruction.
Reset signal generation sets these registers to 00H.
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