CHAPTER 23 POWER-ON-CLEAR CIRCUIT
User’s Manual U17260EJ6V0UD
542
Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
and Low-Voltage Detector (1/2)
(1) In 1.59 V POC mode (option byte: POCMODE = 0)
Note 4
Internal high-speed
oscillation clock (fRH)
High-speed
system clock (fXH)
(when X1 oscillation
is selected)
Starting oscillation is
specified by software.
Operation
stops
Wait for voltage
stabilization
(1.93 to 5.39 ms)
Normal operation
(internal high-speed
oscillation clock)Note 5
Operation stops
Reset period
(oscillation
stop)
Reset period
(oscillation
stop)
Wait for oscillation
accuracy stabilization
(86 to 361 s)
Normal operation
(internal high-speed
oscillation clock)Note 5
Starting oscillation is
specified by software.
Starting oscillation is
specified by software.
CPU
0 V
Supply voltage
(VDD)
1.8 VNotes 1, 2, 3
Wait for voltage
stabilization
(1.93 to 5.39 ms)
Normal operation
(internal high-speed
oscillation clock)Note 5
0.5 V/ms (MIN.)
Notes 2, 3
Set LVI to be
used for reset
Set LVI to be
used for reset
Set LVI to be
used for interrupt
Internal reset signal
Reset processing (11 to 45 s)
Reset processing (11 to 45 s)
Reset processing (11 to 45 s)
VPOC = 1.59 V (TYP.)
VLVI
Notes 1.
The guaranteed operation range for the standard and (A) grade products is 1.8 V
≤ VDD ≤ 5.5 V, and
2.7 V
≤ VDD ≤ 5.5 V for the (A2) grade products. To set the voltage range below the guaranteed
operation range to the reset state when the supply voltage falls, use the reset function of the low-
voltage detector, or input a low level to the RESET pin.
2.
With the standard and (A) grade products, if the voltage rises to 1.8 V at a rate slower than 0.5 V/ms
(MIN.) on power application, input a low level to the RESET pin after power application and before the
voltage reaches 1.8 V, or set the 2.7 V/1.59 V POC mode by using an option byte (POCMODE = 1).
3.
With the (A2) grade products, if the voltage rises to 2.7 V at a rate slower than 0.75 V/ms (MIN.) on
power application, input a low level to the RESET pin after power application and before the voltage
reaches 2.7 V.
4.
The internal voltage stabilization time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
5.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse
of the stabilization time.
Caution
Set the low-voltage detector by software after the reset status is released (see CHAPTER 24
LOW-VOLTAGE DETECTOR).
Remark
VLVI: LVI detection voltage
VPOC: POC detection voltage
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