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型号： UPSD3233A-40U6T
厂商： 意法半导体
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
中文描述： 闪存可编程系统设备与8032微控制器核心和64Kbit SRAM的
文件页数： 63/176页
文件大小： 1081K
代理商： UPSD3233A-40U6T
63/176
μ
PSD323X
The timer can be configured for either “timer” or
“counter” operation. In the most typical applica-
tions, it is configured for “timer” operation (C/T2 =
0). “Timer” operation is a little different for Timer 2
when it’s being used as a baud rate generator.
Normally, as a timer it wouldincrement every ma-
chine cycle(thus at the1/6 theCPU clockfrequen-
cy). In the case, the baud rate is given by the
formula:
Mode 1,3 Baud Rate = fosc / (32 x [65536 -
(RCAP2H, RCAP2L)]
where (RCAP2H, RCAP2L) is the content of
RC2H and RC2L taken as a 16-bit unsigned inte-
ger.
Timer 2 alsobe used asthe Baud RateGenerating
Mode. This mode is valid only if RCLK + TCLK = 1
in T2CON or in PCON.
Note:
A roll-over in TH2does not set TF2, and will
not generate an interrupt. Therefore, the Timer in-
terrupt does not have to be disabled when Timer 2
is in the Baud Rate Generator Mode.
Note:
If EXEN2 is set, a 1-to-0 transition in T2EX
will set EXF2 but will not cause a reload from
(RCAP2H, RCAP2L) to (TH2, TL2). Thus when
Timer 2 is in use as a baud rate generator, T2EX
can be used as an extra external interrupt, if de-
sired.
It should be noted that when Timer 2 is running
(TR2 =1) in“timer” function in the Baud RateGen-
erator Mode, one should not try to READ or
WRITE TH2 or TL2. Under these conditions the
timer is being incremented every state time, and
the results of a READ or WRITE may not be accu-
rate. TheRC registers may beread, but should not
be written to, because a WRITE might overlap a
reload and cause WRITE and/or reload errors.
Turn the timer off (clear TR2) before accessingthe
Timer 2 or RC registers, in this case.
More About Mode 0.
Serial data enters and exits
through RxD.TxD outputs the shift clock. 8 bits are
transmitted/received: 8 data bits (LSB first). The
baud rate is fixed a 1/6 the CPU clock frequency.
Figure 27, page 65 shows a simplified functional
diagram of the serial port inMode 0, and associat-
ed timing.
Transmission is initiated by any instruction that
uses SBUF as a destination register. The “WRITE
to SBUF” signal at S6P2 also loads a ’1’ into the
9th position of the transmit shift register and tells
the TX Controlblock to commence a transmission.
The internal timing is such that one full machine
cycle will elapse between “WRITE to SBUF” and
activation of SEND.
SEND enables the outputof theshift registerto the
alternate out-put function line of RxD and also en-
able SHIFT CLOCK to the alternate output func-
tion line of TxD. SHIFT CLOCK is low during S3,
S4, and S5 of every machine cycle, and high dur-
ing S6, S1, and S2. At S6P2 of every machine cy-
cle in which SEND is active, the contents of the
transmit shift are shifted to the right one position.
As data bits shift out to the right, zeros come in
from the left. When the MSB of the data byte is at
the output position of the shift register, then the ’1’
that was initially loaded into the 9th position, isjust
to the left of the MSB, and all positions to the left
of that contain zeros. This condition flags the TX
Control block to do one last shift and then deacti-
vateSEND andset T1. Both of these actionsoccur
at S1P1. Both of these actions occur at S1P1 of
the 10th machine cycle after “WRITE to SBUF.”
Reception is initiated by the condition REN= 1 and
R1 = 0. At S6P2 ofthe next machine cycle, the RX
Control unitwrites thebits 11111110 to thereceive
shift register, and in the next clock phaseactivates
RECEIVE.
RECEIVE enables SHIFT CLOCK to the alternate
output function line of TxD. SHIFT CLOCK makes
transitions at S3P1 and S6P1 of every machine
cycle in which RECEIVE is active, the contents of
the receive shift register are shifted to the left one
position. The value that comes in from the right is
the value that wassampled at the RxD pinat S5P2
of the same machine cycle.
As data bits come in from the right, ’1s’shift out to
the left. When the ’0’ that was initially loaded into
the right-most position arrives at the left-most po-
sition in the shift register, it flags the RX Control
block to do one last shift and load SBUF. At S1P1
of the 10th machine cycle after the WRITE to
SCON that cleared RI, RECEIVE is cleared as RI
is set.
More About Mode 1.
Ten bits are transmitted
(through TxD), or received (through RxD): a start
Bit (0),8 data bits (LSB first).and aStop Bit(1). On
receive, the Stop Bit goes into RB8 in SCON. In
the
μ
PSD323X Devices the baud rate is deter-
mined by the Timer 1 over-flow rate.
Figure 29 shows a simplified functional diagram of
the serial port in Mode 1, and associated timings
for transmit receive.
Transmission is initiated by any instruction that
uses SBUF as a destination register. The “WRITE
to SBUF” signal also loads a ’1’into the 9th bit po-
sition of thetransmit shift register and flags the TX
Control unit that a transmission is requested.
Transmission actually commences at S1P1 of the
machine cycle following the next rollover in the di-
vide-by-16 counter. (Thus, the bit times are syn-
chronized to the divide-by-16 counter, not to the
“WRITE to SBUF” signal.)
The transmission begins with activation of SEND
which puts the start bit at TxD. One bit time later,
DATA is activated, which enables the output bit of
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