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参数资料
| 型号： | V827432K24SAEX-B1 |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封装： | LEAD FREE, DIMM-184 |
| 文件页数： | 13/16页 |
| 文件大小： | 253K |
| 代理商： | V827432K24SAEX-B1 |
6
ProMOS TECHNOLOGIES
V827432K24SA
V827432K24SA Rev. 1.0 December 2003
24
DDR SDRAM Access time from 2nd highest CL
±0.8
ns
±0.75
ns
±0.75
ns
±0.70
ns
±0.65
ns
±0.70
ns
±0.70
ns
80h
75h
70h
65h
70h
25
DDR SDRAM cycle time at 3rd highest CL
-
7.5ns 7.5ns 7.5ns
00h
75h
26
DDR SDRAM Access time from 3rd highest CL
-
±0.75
ns
±0.75
ns
±0.75
ns
00h
75h
27
Minimum row precharge time (=tRP)
20ns 20ns 15ns 18ns 15ns 15ns 20ns 50h
50h 3Ch 48h 3Ch 3Ch 50h
28
Minimum row activate to row active delay(=tRRD) 15ns 15ns 15ns 12ns 10ns 10ns 10ns 3Ch 3Ch 3Ch 30h 28h 28h 28h
29
Minimum RAS to CAS delay(=tRCD)
20ns 20ns 15ns 18ns 15ns 15ns 20ns 50h
50h 3Ch 48h 3Ch 3Ch 50h
30
Minimum active to precharge time(=tRAS)
50ns 45ns 45ns 42ns 40ns 40ns 40ns 32h 2Dh 2Dh 2Ah
28h
31
Module ROW density
256MB
40h
32
Command and address signal input setup time
1.1ns 0.9ns 0.9ns 0.75
ns
0.6ns 0.6ns 0.6ns B0h
90h
75h
60h
33
Command and address signal input hold time
1.1ns 0.9ns 0.9ns 0.75
ns
0.6ns 0.6ns 0.6ns B0h
90h
75h
60h
34
Data signal input setup time
0.6ns 0.5ns 0.5ns 0.45
ns
0.4ns 0.4ns 0.4ns 60h
50h
45h
40h
35
Data signal input hold time
0.6ns 0.5ns 0.5ns 0.45
ns
0.4ns 0.4ns 0.4ns 60h
50h
45h
40h
36-40 Superset information (may be used in future)
00h
41
SDRAM device minimum active to active/auto-re-
fresh time
(=tRC)
70ns 65ns 65ns 60ns 60ns 60ns 60ns 46h
41h
41h 3Ch 3Ch 3Ch 3Ch
42
SDRAM device minimum active to autorefresh to
active/auto-refresh time (=tRFC)
80ns 75ns 75ns 72ns 70ns 70ns 70ns 50h
4Bh 4Bh
48h
46h
43
SDRAM device maximum device cycle time (=tCK
MAX)
12ns 12ns 12ns 12ns 12ns 12ns 12ns 30h
30h
44
SDRAM device maximum skew between DQS
and DQ signals (=tDQSQ)
0.6ns 0.5ns 0.5ns 0.45n
s
0.4ns 0.4ns 0.4ns 3Ch 32h
32h 2Dh 28h
28h
45
SDRAM device maximum read datahold skew
factor (=tQHS)
1ns 0.75n
s
0.75n
s
0.60n
s
0.55
ns
0.55
ns
0.55
ns
A0h
75h
60h
55h
46-61 Superset information (may be used in future)
-
00h
62
SPD data revision code
Initial release
00h
11h
63
Checksum for Bytes 0 ~ 62
-
F9h
34h DCh 5Dh B5h D0h F8h
64
Manufacturer JEDEC ID code
ProMOS
40h
65 -71 ....... Manufacturer JEDEC ID code
00h
Byte
#
Function described
Function Supported
Hex value
A1
B0
B1
C0
D0
D3
D4
A1
B0
B1
C0
D0
D3
D4
Serial Presence Detect Information (cont.)
相关PDF资料 |
PDF描述 |
|---|---|
| V827432K24S | 2.5 VOLT 32M x 72 HIGH PERFORMANCE UNBUFFERED ECC DDR SDRAM MODULE |
| V85ECADBFREQ | VCXO, CLOCK, 1.5 MHz - 200 MHz, HCMOS OUTPUT |
| V85ECBDAFREQ | VCXO, CLOCK, 1.5 MHz - 200 MHz, HCMOS OUTPUT |
| V85ECBDBFREQ | VCXO, CLOCK, 1.5 MHz - 200 MHz, HCMOS OUTPUT |
| V85EDBCAFREQ | VCXO, CLOCK, 1.5 MHz - 200 MHz, HCMOS OUTPUT |
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