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参数资料
| 型号： | V827432K24SAEX-B1 |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封装： | LEAD FREE, DIMM-184 |
| 文件页数： | 4/16页 |
| 文件大小： | 253K |
| 代理商： | V827432K24SAEX-B1 |
12
ProMOS TECHNOLOGIES
V827432K24SA
V827432K24SA Rev. 1.0 December 2003
Notes: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
5. CK, CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed
by design or tester correlation.
7. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
CLK to First Rising edge of
DQS-In
tDQSS 0.72 1.25 0.72 1.25 0.72 1.25 0.75 1.25 0.75
1.25
0.75
1.25
0.75 1.25 CLK
Data-In Setup Time to DQS-
In (DQ & DM)
tDS
0.40
-
0.40
-
0.40
-
0.45
-
0.5
-
0.5
-
0.6
-
ns
7
Data-in Hold Time to DQS-In
(DQ & DM)
tDH
0.40
-
0.40
-
0.40
-
0.45
-
0.5
-
0.5
-
0.6
-
ns
7
DQ & DM Input Pulse Width
tDIPW
1.75
-
1.75
-
1.75
-
1.75
-
1.75
-
1.75
-
2
-
ns
Read DQS Preamble Time
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
CLK
Read DQS Postamble Time
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CLK
Write DQS Preamble Setup
Time
tWPRES
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
Write DQS Preamble Hold
Time
tWPREH 0.25
-
0.25
-
0.25
-
0.25
-
0.25
-
0.25
-
0.25
-
CLK
Write DQS Postamble Time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CLK
Mode Register Set Delay
tMRD
2-
2
-
2-
2
-
2
-
2
-
CLK
Power Down Exit Time to any
command
tXPDN
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Exit Self Refresh to Non-
Read Command
tXSNR
200
-
200
-
200
-
200
-
75
-
75
-
80
-
CLK
Exit Self Refresh to Read
Command
tXSRD
200
-
200
-
200
-
200
-
200
-
200
-
200
-
CLK
8
Average Periodic Refresh In-
terval
tREFI
-
7.8
-
7.8
-
7.8
-
7.8
-
7.8
-
7.8
-
7.8
us
Parameter
Sym-
bol
(DDR400A)
D0
(DDR400B)
D3
(DDR400C)
D4
(DDR333)
C0
(DDR266A)
B1
(DDR266B)
B0
(DDR200)
A1
Unit Note
Min
Max Min
Max
Min
Max Min Max
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