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参数资料
| 型号： | V91F565U24QCFW-F5 |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.45 ns, DMA240 |
| 封装： | ROHS COMPLIANT, FBDIMM-240 |
| 文件页数： | 10/22页 |
| 文件大小： | 207K |
| 代理商： | V91F565U24QCFW-F5 |
V91F565U24QC Rev 1.0 May 2007
18
V91F565U24QC
ProMOS TECHNOLOGIES
AC Characteristics (AC operating conditions unless otherwise noted)
Parameter
Symbol
(DDR2-533)
-E4
(DDR2-667)
-F5
Unit
Min
Max
Min
Max
Row Cycle Time
tRC
60
-
60
-
ns
Auto Refresh Row Cycle Time
tRFC
105
-
105
-
ns
Row Active Time
tRAS
45
70K
45
70K
ns
Row Address to Column Address Delay
tRCD
15
-
15
-
ns
Row Active to Row Active Delay (x4 & x8)
tRRD
7.5
-
7.5
-
ns
Row Active to Row Active Delay (x16)
tRRD
10
-
10
-
ns
Column Address to Column Address Delay
tCCD
2-
2
-
CLK
Row Precharge Time
tRP
15
-
15
-
ns
Write Recovery Time
tWR
15
-
15
-
ns
Last Data-In to Read Command
tDRL
1
-
1
-
CLK
Auto Precharge Write Recovery + Precharge Time
tDAL
tWR +tRP
-
tWR +tRP
-
ns
System Clock Cycle Time
CAS Latency = 3
tCK
58
5
8
ns
CAS Latency = 4
3.75
8
3.75
8
ns
CAS Latency = 5
3.75
8
3
8
ns
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
CLK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
CLK
Data-Out edge to Clock edge Skew
tAC
-0.50
0.50
-0.45
0.45
ns
DQS-Out edge to Clock edge Skew
tDQSCK
-0.45
0.45
-0.40
0.40
ns
DQS-Out edge to Data-Out edge Skew
tDQSQ
-
0.30
-
0.25
ns
Data-Out hold time from DQS
tQH
tHPmin
-tQHS
-
tHPmin
-tQHS
-
ns
Data hold skew factor
tQHS
-
400
-
350
ps
Clock Half Period
tHP
tCH/L
min
-
tCH/L
min
-
ns
Input Setup Time (fast slew rate)
tIS
250
-
200
-
ps
Input Hold Time (fast slew rate)
tIH
375
-
325
-
ps
Input Pulse Width
tIPW
0.35
-
0.35
-
CLK
Write DQS High Level Width
tDQSH
0.35
CLK
Write DQS Low Level Width
tDQSL
0.35
CLK
CLK to First Rising edge of DQS-In
tDQSS
WL-0.25tCK
WL+
0.25tCK
WL-0.25tCK
WL+
0.25tCK
CLK
Data-In Setup Time to DQS-In (DQ & DM)
tDS
100
-
50
-
ps
Data-in Hold Time to DQS-In (DQ & DM)
tDH
225
-
175
-
ps
DQS falling edge to CLK rising Setup Time
tDSS
0.2
-
0.2
-
CLK
DQS falling edge from CLK rising Hold Time
tDSH
0.2
-
0.2
-
CLK
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