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参数资料
| 型号： | V91F565U24QCFW-F5 |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.45 ns, DMA240 |
| 封装： | ROHS COMPLIANT, FBDIMM-240 |
| 文件页数： | 6/22页 |
| 文件大小： | 207K |
| 代理商： | V91F565U24QCFW-F5 |
V91F565U24QC Rev 1.0 May 2007
14
V91F565U24QC
ProMOS TECHNOLOGIES
Differential Receiver Input Specifications
Notes :
1. Specified at the package pins into a timing and voltage compliant test setup. Note that signal levels at the pad will be lower than at the
pin.
2. Single-ended voltages below that value that are simultaneously detected on D+ and D-are interpreted as the Electrical Idle condition.
Worst-case margins are determined for the case with transmitter using small voltage swing.
3. Multiple lanes need to detect the El condition before the device can act upon the El detection.
4. Specified at the package pins into a timing and voltage compliance test setup.
5. The single-pulse mask provides suffcient symbol energy for reliable RX reception. Each symbol must comply with both the single-pulse
mask and the cumulative eyemask.
6. The relative amplitude ratio limit between adjacent symbols prevents excessive intersymbol interference in the RX. Each symbol must
comply with the peak amplitude ratio with regard to both the preceding and subsequent symbols.
7. This number does not include the effects of SSC or reference clock jitter.
8. This number includes setup and hold of the RX sampling flop.
9. Defined as the dual-dirac deterministic timing error.
10. Allows for 15 mV DC offset between transmit and receive devices.
Parameter
Symbol
Values
Units
Comments
MIN
MAX
Differential peak-to-peak input voltage for
large voltage swing
VRX-DIFFp-p
170
TBD
mV
EQ 5, Note1
Maximum single-ended voltage in El condition
VRX-IDLE-SE
75
mV
2,3
Maximum single-ended voltage in Ei condition
(DC only)
VRX-IDLE-SE-DC
50
mV
2,3
Maximum peak-to-peak differential voltage in
El condition
VRX-IDLE-DIFFp-p
65
mV
3
Single-ended voltage (w.r.t. VSS) on D+/D-
VRX-SE
-300
900
mV
4
Single-pulse peak differential input voltage
VRX-DIFF-PULSE
85
mV
4,5
Amplitude ratio between adjacent symbols
VRX-DIFF-ADJ-RATIO
TBD
4,6
Maximum RX inherent timing error, 3.2 and
4.0 Gb/x
TRX-TJ-MAX
0.4
UI
4,7,8
Maximum RX inherent deterministic timing er-
or, 3.2 and 4.8 Gb/s
TRX-TJ-MAX4.8
TBD
UI
4,7,8
Single-pulse width as zero-voltage crossing
VRX-DJ-DD
0.3
UI
4,7,8,9
Skingle-pulse width at minimum-level cross-
ing
VRX-DJ-DD-4.8
TBD
UI
4,7,8,9
Differential RX input rise/fall time
TRX-PW-ZC
0.55
UI
4,5
common mode fo the input voltage
TRX-PW-ML
0.2
UI
4.5
Differential RX output rise/fall time
TRX-RISE TRX-FALL
50
ps
20~80% voltage
Common mode of input voltage
VRX-CM
120
400
mV
EQ 6, Note1, 10
AC peak-to-peak common mode of input volt-
age
VRX-CM-ACp-p
270
mV
EQ 7, Note 1
Ratio of VRX-CM-ACp-p to minimum VRX-DIFFp-p
VRX-CM-EH-RATOP
45
%
11
Differential return loss
RLRX-DIFF
9
dB
1GHz-2.4 GHz, Note 12
Common mode return loss
RLRX-CM
6
dB
1GHz-2.4 GHz, Note 12
RX termination impedance
RRX
41
55
13
D+/D- RX Impedance difference
RRX-MATCH-DC
4%
EQ
8
Lane-to lane PCB skew at RX
LRX-PCB-SKEW
6UI
Lane-to-lane skew at the receiver
that must be tolerated. Note 14
Minimum RX drift tolerance
TRX-DRIFT
400
ps
15
Minim data tracking 3dB bandwidth
FTRK
0.2
MHz
16
Electrical idle entry detect time
TEI-ENTRY-DETECT
60
ns
17
Electrical idle exit detect time
TEI-EXIT-DETECT
30
ns
Bit Error Ratio
BER
10-12
18
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