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| 型号： | V91F565U24QCFW-F5 |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.45 ns, DMA240 |
| 封装： | ROHS COMPLIANT, FBDIMM-240 |
| 文件页数： | 7/22页 |
| 文件大小： | 207K |
| 代理商： | V91F565U24QCFW-F5 |
V91F565U24QC Rev 1.0 May 2007
15
V91F565U24QC
ProMOS TECHNOLOGIES
11. The received differential signal must satisfy both this ratio as well as the absolute maximum AC peaktopeak common mode spec-
ification. For example, if VRX-DIFFp-p is 200 mV, the maximum AC peak-to peak common mode is the lesser of (200 mV*0.45=90
mV)and VRX-CM-AC-p-p.
12. One of the components that contribute to the deterioration of the return loss is the ESD structure which needs to be carefully de-
signed.
13. The termination small signal resistance; tolerance across voltage from 100 mV to 400 mV shall not exceed +/-5 W with regard to
the average of the values measured at 100 mV and at 400 mV for that pin.
14. This number represents the lane-to-lane skew between TX and RX pins and does not include the transmitter output skew from the
component of the end-to-end channel skew in the AMB specification.
15. Measured from the reference clock edge to the center of the input eye. This specification must be met across specified voltage and
temperature ranges for a single component. Drift rate of change is significantly below the tracking capability of the receiver.
16. This bandwidth number assume the specified minimum data transition density. Maximum jitter at 0.2 MHz is 0.05 UI,
17. The specified time includes the time required to forward the El entry condition.
18. BER per differential lane.
VRX-DIFFp-p = 2x[VRX-D+-VRX-D-] (EQ5)
(VRX-CM = DC(avg) of [VRX-D+ + VRX-D-] /2) (EQ 6)
VRX-CM-AC=((Max[VRX-D+ + VRX-D)/2)((Min [VRX-D+ + VRX-D-)/2) (EQ 7)
RRX-MATCH-DC = 2x((RRX-D+-RRX-D-)/(RRX-D+ + RRX-D-) (EQ 8)
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