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| 型号： | VNC2-64Q1B-TRAY |
| 厂商： | FTDI, Future Technology Devices International Ltd |
| 文件页数： | 22/88页 |
| 文件大小： | 0K |
| 描述： | IC USB HOST/DEVICE CTRL 64-QFN |
| 应用说明： | Vinculum-II IO Cell Description AppNote Vinculum-II Debug Interface Description AppNote Vinculum-II IO Mux Explained AppNote Vinculum-II PWM Example AppNote Migrating Vinculum Designs AppNote |
| 标准包装： | 260 |
| 系列： | Vinculum-II |
| 控制器类型： | USB 2.0 控制器 |
| 接口： | USB，主机/设备配置，UART，SPI，PWM，闪存 256K，DMA 4CH |
| 电源电压： | 1.62 V ~ 1.98 V |
| 电流 - 电源： | 25mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘 |
| 供应商设备封装： | 64-QFN（8x8） |
| 包装： | 托盘 |
| 其它名称： | VNC2-64Q1A-TRAY VNC2-64Q1A-TRAY-ND |
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Copyright 2009-2011 Future Technology Devices International Limited
Datasheet
Vinculum-II Embedded Dual USB Host Controller IC
Version 1.5
Document No.: FT_000138 Clearance No.: FTDI# 143
5.1 I/O Peripherals Signal Names
Peripheral
Signal Name
Outputs
Inputs
Description
Debugger
debug_if
1
debugger interface
UART
uart_txd
1
0
Transmit asynchronous data output
uart_rts#
1
0
Request to send control output
uart_dtr#
1
0
Data acknowledge (data terminal ready control) output
uart_tx_active
1
0
Enable transmit data for RS485 designs
uart_rxd
0
1
Receive asynchronous data input
uart_cts#
0
1
Clear to send control input
uart_dsr#
0
1
Data request (data set ready control) input
uart_ri#
0
1
Ring indicator control input
uart_dcd#
0
1
Data carrier detect control input
FIFO
fifo_data
8
FIFO data bus
fifo_txe#
1
0
When high, do not write data into the FIFO. When low,
data can be written into the FIFO by strobing WR high,
then low.
fifo_rxf#
1
0
When high, do not read data from the FIFO. When low,
there is data available in the FIFO which can be read by
strobing RD# low, then high.
fifo_wr#
0
1
Writes the data byte on the D0...D7 pins into the
transmit FIFO buffer when WR goes from high to low.
fifo_rd#
0
1
Enables the current FIFO data byte on D0...D7 when low.
Fetches the next FIFO data byte (if available) from the
receive FIFO buffer when RD# goes from high to low
fifo_oe#
0
1
FIFO output enable – synchronous FIFO only
fifo_clkout
0
1
FIFO clock out – synchronous FIFO only
GPIO
gpio
40
General purpose I/O
SPI Slave 0
spi_s0_clk
0
1
SPI clock input – slave 0
spi_s0_ss#
0
1
SPI chip select input – slave 0
spi_s0_mosi
1
SPI master out serial in – slave 0
spi_s0_miso
1
0
SPI master in slave out – slave 0
SPI Slave 1
spi_s1_clk
0
1
SPI clock input – slave 1
spi_s1_ss#
0
1
SPI chip select input – slave 1
spi_s1_mosi
1
Master out slave in – slave 1
spi_s1_miso
1
0
Master in slave out – slave 1
SPI Master
spi_m_clk
1
0
SPI clock input – master
spi_m_mosi
1
Master out slave in - master
spi_m_miso
0
1
Master in slave out - master
spi_m_ss_0#
1
0
Active low slave select 0 from master to slave 0
spi_m_ss_1#
1
0
Active low slave select 1 from master to slave 1
PWM
pwm
8
0
Pulse width modulation
Table 5.1 I/O Peripherals Signal Names
Note: # is used to indicate an active low signal.
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