- 您现在的位置：买卖IC网 > PDF目录16113 > VTERB-BLK-E3-U4 (Lattice Semiconductor Corporation)IP CORE VITERBI DECODER ECP3 PDF资料下载
参数资料
| 型号： | VTERB-BLK-E3-U4 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 10/34页 |
| 文件大小： | 0K |
| 描述： | IP CORE VITERBI DECODER ECP3 |
| 产品培训模块： | LatticeECP3 Introduction |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | VTERBBLKE3U4 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页当前第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页
Lattice Semiconductor
Functional Description
Add, Compare, and Select Unit (ACS)
The ACS unit adds the current metric to the accumulated metric for each path and also determines the least metric
for each state of the trellis. The accumulated metric is fetched from register files and stored back there, after adding
the current metric. ACS also writes the survivor trellis path (the previous state information) in memory.
Traceback Unit (TBU)
The TBU performs decoding of the received data by tracing back the trellis from an appropriate starting node.
Traceback and decoding is performed on a block of sequential nodes whose length is equal to the parameter Trace-
back Length. The Viterbi Decoder IP supports both one and two traceback schemes. In the one traceback scheme,
the traceback starts from node 0 and happens for length L, where L is the traceback length. In the two traceback
scheme, the first traceback starts from node 0 and happens for length L. This traceback determines a reliable start-
ing node for the second traceback process. The second traceback starts from this reliable start node and happens
for another length L.
The number of tracebacks employed and the traceback length are mostly set by the user, but the choice is
restricted by other parameters and rules, as imposed by the Block Viterbi Decoder IP GUI.
Memory (MEM)
The memory stores the accumulated metric and the previous state information (traceback information).
Memory Management Unit (MMU)
The MMU generates addresses and read write signals for the memory during different phases of operation.
Bit Error Rate Monitor (BER)
This optional module is used to estimate the bit error rate of the channel. This is achieved by encoding the decoded
output symbols using the same generator polynomials and comparing them with delayed input to the Viterbi
decoder. Assuming the error in decoding is zero or negligible, the error determined by BER is equal to the channel
error.
Other Modules
In Zero Flushing block decoding, an additional module called “Zero Padding Unit” is used. When the block length is
not a multiple of the traceback length, the Zero Padding Unit automatically adds zero samples at the end of each
block of input data.
Configuring the Block Viterbi Decoder
Puncture Settings
The Viterbi Decoder can be configured as a punctured or non-punctured decoder. A punctured decoder actually
decodes convolutional codes that have been punctured after encoding. The puncture settings consist of the punc-
ture block size (this is derived from code rate) and puncture patterns, PP0 and PP1 . The puncture settings are
either fixed using the parameters in the IP GUI or can be dynamically set using input the ports, inrate , outrate ,
pp0 , pp1 and ppset . The values in inrate and outrate correspond to the rate factors k and n , respectively and
they result in a code rate of k / n . The numerator of the code rate representation, k or the inrate is also called as
the puncture block size in this document.
Continuous and Block Decoding
The decoding process can be applied on either continuous stream or blocks of input data. The main difference
between these modes lies in the way the decoder performs the traceback operation. When the decoder is config-
ured in continuous mode, it always performs two length-L tracebacks. The actual traceback length is set by the user
through the IP GUI.
IPUG32_02.7, June 2010
10
Block Viterbi Decoder User’s Guide
相关PDF资料 |
PDF描述 |
|---|---|
| M3BYK-3406R | IDC CABLE - MSR34K/MC34M/MPD34K |
| 160PK22MEFC10X12.5 | CAP ALUM 22UF 160V 20% RADIAL |
| 115101-19-36.00 | CABLE BNC ST PLUG-PLUG RG-58 36" |
| M3DRK-3406R | IDC CABLE - MKR34K/MC34M/MPR34K |
| VTERB-BLK-E2-U4 | IP CORE VITERBI DECODER EC/ECP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| VTERB-BLK-E3-UT4 | 功能描述:开发软件 BLOCK VITERBI DECODER (ECP3) RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| VTERB-BLK-P2-U4 | 功能描述:编码器、解码器、复用器和解复用器 Block Viterbi Decoder RoHS:否 制造商:Micrel 产品:Multiplexers 逻辑系列:CMOS 位数: 线路数量（输入/输出）:2 / 12 传播延迟时间:350 ps, 400 ps 电源电压-最大:2.625 V, 3.6 V 电源电压-最小:2.375 V, 3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Tray |
| VTERB-BLK-PM-U4 | 功能描述:开发软件 Blck Viterbi Decodr User Config RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| VTERB-BLK-SC-U4 | 功能描述:编码器、解码器、复用器和解复用器 Block Viterbi Decoder RoHS:否 制造商:Micrel 产品:Multiplexers 逻辑系列:CMOS 位数: 线路数量（输入/输出）:2 / 12 传播延迟时间:350 ps, 400 ps 电源电压-最大:2.625 V, 3.6 V 电源电压-最小:2.375 V, 3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Tray |
| VTERB-BLK-X2-U4 | 功能描述:开发软件 Blck Viterbi Decodr User Config RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
发布紧急采购，3分钟左右您将得到回复。