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参数资料
| 型号： | VTERB-BLK-E3-U4 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 21/34页 |
| 文件大小： | 0K |
| 描述： | IP CORE VITERBI DECODER ECP3 |
| 产品培训模块： | LatticeECP3 Introduction |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | VTERBBLKE3U4 |
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Lattice Semiconductor
Parameter Settings
GP0, GP1, GP2, GP3, GP4, GP5, GP6
Generator polynomials used for generating the convolutional code. Two polynomials are always used for punctured
decoders (either fixed or dynamic). For non-punctured decoders, the number of polynomials used is equal to n,
where n is denominator of the Code Rate (k/n).The width of each polynomial is equal to constraint length, K.
Implementation Method
The implementation method can be either “parallel” or “hybrid”. In the parallel implementation, the decoder can pro-
duce one output data in one cycle. In hybrid implementations, it takes multiple clock cycles to generate each output
data, but a smaller number of device resources are used.
Hybrid Index
This controls the resource-throughput trade-off in hybrid implementations. It takes 2 Hybrid Index cycles to produce one
output data.
Inputs
Decoder Input
Specifies whether the decoder is fed with a hard decision or soft decision input. For punctured decoders, this option
is not available and decoder has to be fed with soft decision inputs.
Soft Width
Input data width for soft decision inputs.
Data Type
Specifies whether the input data type is represented in sign-magnitude form (signed) or unsigned offset form
(unsigned). See the section “configuring the Block Viterbi Decoder” for details.
BER (Bit Error Rate)
BER Monitor
Specifies whether the optional bit error rate (BER) monitor is added to the Viterbi decoder.
BER Period
This determines the duration for which the BER is accumulated. The BER value starts accumulating from zero for
up to 2^(BER Period) clock cycles. After this period, the accumulated value is placed on the BER output port. The
BER value is then reset and the monitor starts accumulating again.
IPUG32_02.7, June 2010
21
Block Viterbi Decoder User’s Guide
相关PDF资料 |
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| VTERB-BLK-E2-U4 | IP CORE VITERBI DECODER EC/ECP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| VTERB-BLK-E3-UT4 | 功能描述:开发软件 BLOCK VITERBI DECODER (ECP3) RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| VTERB-BLK-P2-U4 | 功能描述:编码器、解码器、复用器和解复用器 Block Viterbi Decoder RoHS:否 制造商:Micrel 产品:Multiplexers 逻辑系列:CMOS 位数: 线路数量（输入/输出）:2 / 12 传播延迟时间:350 ps, 400 ps 电源电压-最大:2.625 V, 3.6 V 电源电压-最小:2.375 V, 3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Tray |
| VTERB-BLK-PM-U4 | 功能描述:开发软件 Blck Viterbi Decodr User Config RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| VTERB-BLK-SC-U4 | 功能描述:编码器、解码器、复用器和解复用器 Block Viterbi Decoder RoHS:否 制造商:Micrel 产品:Multiplexers 逻辑系列:CMOS 位数: 线路数量（输入/输出）:2 / 12 传播延迟时间:350 ps, 400 ps 电源电压-最大:2.625 V, 3.6 V 电源电压-最小:2.375 V, 3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Tray |
| VTERB-BLK-X2-U4 | 功能描述:开发软件 Blck Viterbi Decodr User Config RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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