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| 型号： | W28J161TB90L |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 1M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| 封装： | 8 X 8 MM, 0.75 MM PITCH, TFBGA-48 |
| 文件页数： | 11/43页 |
| 文件大小： | 1333K |
| 代理商： | W28J161TB90L |
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W28J161B/T
Publication Release Date: April 7, 2003
- 19 -
Revision A4
Table 6. Status Register Definition
WSMS
BESS
ECBLBS
WWSLBS
VPPS
WWSS
DPS
R
7
6
5
4
3
2
1
0
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS STATUS
(ECBLBS)
1 = Error in Block Erase, Full Chip Erase or Clear Block
Lock-Bits
0 = Successful Block Erase, Full Chip Erase or Clear
Block Lock-Bits
SR.4 = WORD WRITE AND SET LOCK-BIT STATUS
(WWSLBS)
1 = Error in Word Write or Set Block/Permanent Lock-Bit
0 = Successful Word Write or Set Block/Permanent Lock-
Bit
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR.2 = WORD WRITE SUSPEND STATUS (WWSS)
1 = Word Write Suspended
0 = Word Write in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Block Lock-Bit, Permanent Lock-Bit and/or #WP Lock
Detected, Operation Abort
0 = Unlock
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Notes:
Check SR.7 to determine block erase, full chip erase, word
write or lock-bit configuration completion. SR.6-0 are invalid
while SR.7 = "0".
If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase or lock-bit configuration attempt, an improper
command sequence was entered.
SR.3 does not provide a continuous indication of VPP level.
The WSM interrogates and indicates the VPP level only after
Block Erase, Full Chip Erase, Word Write or Lock-Bit
Configuration command sequences. SR.3 is not
guaranteed to reports accurate feedback only when VPP ≠
VPPH1/2.
SR.1 does not provide a continuous indication of
permanent and block lock-bit and #WP values. The WSM
interrogates the permanent lock-bit, block lock-bit and #WP
only after Block Erase, Full Chip Erase, Word Write or
Lock-Bit Configuration command sequences. It informs the
system, depending on the attempted operation, if the block
lock-bit is set, permanent lock-bit is set and/or #WP is VIL.
Reading the block lock and permanent lock configuration
codes after writing the Read Identifier Codes command
indicates permanent and block lock-bit status.
SR.0 is reserved for future use and should be masked out
when polling the status register.
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