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参数资料
| 型号： | W28J161TB90L |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 1M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| 封装： | 8 X 8 MM, 0.75 MM PITCH, TFBGA-48 |
| 文件页数： | 5/43页 |
| 文件大小： | 1333K |
| 代理商： | W28J161TB90L |
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W28J161B/T
Publication Release Date: April 7, 2003
- 13 -
Revision A4
Read Array Command
Upon initial device power-up and after exit from reset mode, the device defaults to read array mode.
This operation is also initiated by writing the Read Array command. The device remains enabled for
reads until another command is written. Once the internal WSM has started a block erase, full chip
erase, word write or lock-bit configuration the device will not recognize the Read Array command until
the WSM completes its operation unless the WSM is suspended via an Erase Suspend or Word Write
Suspend command. The Read Array command functions independently of the VPP voltage and
#RESET can be VIH.
Read Identifier Codes Command
The identifier code operation is initiated by writing the Read Identifier Codes command. Following the
command write, read cycles from addresses shown in Figure 4 retrieve the manufacturer, device,
block lock configuration and permanent lock configuration codes (see Table 4 for identifier code
values). To terminate the operation, write another valid command. Like the Read Array command, the
Read Identifier Codes command functions independently of the VPP voltage and #RESET can be VIH.
Following the Read Identifier Codes command, the following information can be read:
Table 4. Identifier Codes
CODE
ADDRESS
[A19
A0]
DATA
[DQ15
DQ0]
Manufacture Code
00000H
00B0H
Top Boot
00E8H
Device Code
Bottom Boot
00001H
00E9H
DQ0 = 0
DQ0 = 1
Block Lock Configuration
Block is Unlocked
Block is Locked
Reserved for Future Use
BA(1)+2
DQ1
15
DQ0 = 0
DQ0 = 1
Permanent Lock Configuration
Device is Unlocked
Device is Locked ed
Reserved for Future Use
00003H
DQ1
15
Note: BA selects the specific block lock configuration code to be read. See Figure 4 for the device identifier code memory map.
Read Status Register Command
The status register may be read to determine when a block erase, full chip erase, word write or lock-
bit configuration is complete and whether the operation completed successfully. It may be read at any
time by writing the Read Status Register command. After writing this command, all subsequent read
operations output data from the status register until another valid command is written. The status
register contents are latched on the falling edge of #OE or #CE, whichever occurs last. #OE or #CE
must toggle to VIH before further reads to update the status register latch. The Read Status Register
command functions independently of the VPP voltage. #RESET can be VIH.
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