- 您现在的位置：买卖IC网 > PDF目录68449 > W28J161TB90L (WINBOND ELECTRONICS CORP) 1M X 16 FLASH 3V PROM, 90 ns, PBGA48 PDF资料下载
参数资料
| 型号： | W28J161TB90L |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 1M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| 封装： | 8 X 8 MM, 0.75 MM PITCH, TFBGA-48 |
| 文件页数： | 9/43页 |
| 文件大小： | 1333K |
| 代理商： | W28J161TB90L |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页
W28J161B/T
Publication Release Date: April 7, 2003
- 17 -
Revision A4
When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The CUI will remain in read status register mode until
a new command is issued.
This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set.
An invalid Set Block or Permanent Lock-Bit command will result in status register bits SR.4 and SR.5
being set to "1". Also, reliable operations occur only when VDD = 2.7V to 3.6V and VPP = VPPH1/2. In the
absence of this high voltage, lock-bit contents are protected against alteration.
A successful set block lock-bit operation requires that the permanent lock-bit be cleared. If it is
attempted with the permanent lock-bit set, SR.1 and SR.4 will be set to "1" and the operation will fail.
Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. If the permanent
lock-bit is not set, block lock-bits can be cleared using only the Clear Block Lock-Bits command. If the
permanent lock-bit is set, block lock-bits cannot be cleared. See Table 5 for a summary of hardware
and software write protection options.
Clear block lock-bits operation is executed by a two-cycle command sequence. A clear block lock-bits
setup is first written. After the command is written, the device automatically outputs status register
data when read (see Figure 11). The CPU can detect completion of the clear block lock-bits event by
reading the status register bit SR.7.
When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bit
error is detected, the status register should be cleared. The CUI will remain in read status register
mode until another command is issued.
This two-step sequence of set-up followed by execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status register
bits SR.4 and SR.5 being set to "1". Also, a reliable clear block lock-bits operation can only occur
when VDD = 2.7V to 3.6V and VPP = VPPH1/2. If a clear block lock-bits operation is attempted while VPP ≤
VPPLK, SR.3 and SR.5 will be set to "1". In the absence of this high voltage, the block lock-bits content
are protected against alteration. A successful clear block lock-bits operation requires that the
permanent lock-bit is not set. If it is attempted with the permanent lock-bit set, SR.1 and SR.5 will be
set to "1" and the operation will fail.
If a clear block lock-bits operation is aborted due to VPP or VDD transitioning out of valid range or
#RESET active transition, block lock-bit values are left in an undetermined state. A repeat of clear
block lock-bits is required to initialize block lock-bit contents to known values. Once the permanent
lock-bit is set, it cannot be cleared.
Block Locking by the #WP
This Boot Block Flash memory architecture features two hardware-lockable boot blocks so that the
kernel code for the system can be kept secure while other blocks are programmed or erased as
necessary.
The lockable two boot blocks are locked when #WP = VIL; any program or erase operation to a locked
block will result in an error, which will be reflected in the status register. For top configuration, the top
two boot blocks are lockable. For the bottom configuration, the bottom two boot blocks are lockable. If
#WP is VIH and block lock-bit is not set, boot block can be programmed or erased normally (Unless
VPP is below VPPLK). #WP is valid only two boot blocks, other blocks are not affected.
相关PDF资料 |
PDF描述 |
|---|---|
| W28J161BB90L | 1M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| W28J321BB90L | 2M X 16 FLASH 2.7V PROM, 90 ns, PBGA48 |
| W29C010MP90B | 128K X 8 FLASH 5V PROM, 90 ns, PQCC32 |
| W29C010MP90 | 128K X 8 FLASH 5V PROM, 90 ns, PQCC32 |
| W29C011AP15N | 128K X 8 FLASH 5V PROM, 150 ns, PQCC32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W28NK60Z | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:N-CHANNEL 600 V - 0.155з - 27A TO-247 Zener-Protected SuperMESH MOSFET |
| W28-SQ11A-10 | 功能描述:CIRCUIT BREAK 10A W/SWITCH RoHS:否 类别:过电压，电流，温度装置 >> 断路器 系列:W28 标准包装:3 系列:AS168X 断路器类型:热磁动式 电压:65VDC，277/480VAC 电流 - 跳闸(It):30A 极数:3 触动器类型:按片 安装类型:DIN 轨道 其它名称:4420.02104420.0210-ND486-2338AS168X-CB3G300-NDCBE AS168X-CB3G300 |
| W28-SQ11A-15 | 制造商:TE Connectivity 功能描述: |
| W28-SQ11A-3 | 制造商:TE Connectivity 功能描述:Circuit Breaker Thermal 1Pole 3A 250VAC/32VDC |
| W28-SQ11A-5 | 制造商:TE Connectivity 功能描述:Circuit Breaker Thermal 1Pole 5A 250VAC/32VDC |
发布紧急采购，3分钟左右您将得到回复。