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参数资料
| 型号： | W28J320TT90L |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 2M X 16 FLASH 2.7V PROM, 90 ns, PDSO48 |
| 封装： | 12 X 20 MM, TSOP-48 |
| 文件页数： | 11/48页 |
| 文件大小： | 1513K |
| 代理商： | W28J320TT90L |
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W28J320B/T
Publication Release Date: April 11, 2003
- 19 -
Revision A4
level used for block erase) while block erase is suspended. #RESET must also remain at VIH. #WP
must also remain at VIL or VIH (the same #WP level used for block erase). Block erase cannot resume
until word/byte write operations initiated during block erase suspend have completed.
If the time between writing the Block Erase Resume command and writing the Block Erase Suspend
command is shorter than tERES and both commands are written repeatedly, a longer time is required
than standard block erase until the commpletion of the operation.
Word/Byte Write Suspend Command
The Word/Byte Write Suspend command allows word/byte write interruption to read data in other flash
memory locations. Once the word/byte write process starts, sending the Word/Byte Write Suspend
command causes the WSM to suspend the Word/Byte write sequence at a predetermined point in the
algorithm. The device continues to output status register data when read after the Word/Byte Write
Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the
word/byte write operation has been suspended (both will be set to "1"). RY/#BY will also transition to
High Z. The period tWHRZ1 defines the word/byte write suspend latency parameters.
When Word/Byte Write Suspend command writes to the CUI, the device is placed in read array mode
if word/byte write is finished. Therefore, after Word/Byte Write Suspend command writes to the CUI,
the Read Status Register command (70H) has to write to CUI, then status register bit SR.2 should be
checked to confirm the device is in suspend mode.
At this point, a Read Array command can be written to read data from locations other than that which
is suspended. The only other valid commands while word/byte write is suspended are Read Status
Register and Word/Byte Write Resume. After Word/Byte Write Resume command is written to the
flash memory, the WSM will continue the word/byte write process. Status register bits SR.2 and SR.7
will automatically clear and RY/#BY will return to VOL. After the Word/Byte Write Resume command is
written, the device automatically outputs status register data when read (reference Figure 10). VPP
must remain at VPPH1/2 (the same VPP level used for word/byte write) while in word/byte write suspend
mode. #RESET must also remain at VIH. #WP must also remain at VIH or VOL (the same #WP level
used for word/byte write).
If the period from Word/Byte Write Resume command write to Word/Byte Write Suspend command
write is too short, it can be repeated, and the write time will be prolonged.
Set Block and Permanent Lock-Bit Commands
A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits, a
permanent lock-bit and #WP pin. The block lock-bits and #WP pin gates program and erase
operations while the permanent lock-bit gates block-lock bit modification. With the permanent lock-bit
not set, individual block lock-bits can be set via the Set Block Lock-Bit command. The Set Permanent
Lock-Bit command sets the permanent lock-bit. After the permanent lock-bit is set, block lock-bits and
locked block contents cannot be altered. Refer to Table 5 for a summary of hardware and software
write protection options.
Set block lock-bit and permanent lock-bit are executed via a two-cycle command sequence. The set
block or permanent lock-bit setup, along with appropriate block or device address, is written followed
by either the set block lock-bit confirm (and an address within the block to be locked) or the set
permanent lock-bit confirm (and any device address). The WSM then executes the set lock-bit
algorithm. After the sequence is written, the device automatically outputs status register data when
read (reference Figure 11). The CPU can detect the completion of the set lock-bit event by analyzing
the RY/#BY pin output or status register bit SR.7.
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