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参数资料
| 型号： | W28J320TT90L |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 2M X 16 FLASH 2.7V PROM, 90 ns, PDSO48 |
| 封装： | 12 X 20 MM, TSOP-48 |
| 文件页数： | 15/48页 |
| 文件大小： | 1513K |
| 代理商： | W28J320TT90L |
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W28J320B/T
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Table 6. Status Register Definition
WSMS
BESS
ECBLBS
WBWSLBS
VPPS
WBWSS
DPS
R
7
6
5
4
3
2
1
0
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS STATUS
(ECBLBS)
1 = Error in Block Erase, Full Chip Erase or Clear Block
Lock-Bits
0 = Successful Block Erase, Full Chip Erase or Clear
Block Lock-Bits
SR.4 = WORD/BYTE WRITE AND SET LOCK-BIT STATUS
(WBWSLBS)
1 = Error in Word/Byte Write or Set Block/Permanent
Lock-Bit
0 = Successful Word/Byte Write or Set Block/Permanent
Lock-Bit
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR.2 = WORD/BYTE WRITE SUSPEND STATUS (WBWSS)
1 = Word/Byte Write Suspended
0 = Word/Byte Write in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Block Lock-Bit, Permanent Lock-Bit and/or #WP Lock
Detected, Operation Abort
0 = Unlock
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Notes:
Check RY/#BY or SR.7 to determine block erase, full chip
erase, word/byte write or lock-bit configuration completion.
SR.6-0 are invalid while SR.7 = "0".
If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase or lock-bit configuration attempt, an improper
command sequence was entered.
SR.3 does not provide a continuous indication of VPP level.
The WSM interrogates and indicates the VPP level only after
Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit
Configuration command sequences. SR.3 is not guaranteed
to reports accurate feedback only when VPP ≠ VPPh1/2.
SR.1 does not provide a continuous indication of permanent
and block lock-bit and #WP values. The WSM interrogates
the permanent lock-bit, block lock-bit and #WP only after
Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit
Configuration command sequences. It informs the system,
depending on the attempted operation, if the block lock-bit is
set, permanent lock-bit is set and/or #WP is VIL. Reading the
block lock and permanent lock configuration codes after
writing the Read Identifier Codes command indicates
permanent and block lock-bit status.
SR.0 is reserved for future use and should be masked out
when polling the status register.
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