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参数资料
| 型号： | W28J800BT90C |
| 元件分类： | EEPROM |
| 英文描述： | EEPROM |
| 中文描述： | EEPROM的 |
| 文件页数： | 7/51页 |
| 文件大小： | 1468K |
| 代理商： | W28J800BT90C |
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W28J800B/T
6. PIN DESCRIPTION
SYM.
TYPE
NAME AND FUNCTION
A-1
A0
A18
INPUT
ADDRESS INPUTS
: Inputs for addresses during read and write operations. Addresses are
internally latched during a write cycle.
A -1: Lower address input while #BYTE is V
IL
. A-1 pin changes DQ15 pin while #BYTE is V
IH
.
A15
A18: Main Block Address.
A12
A18: Boot and Parameter Block Address.
DQ0
DQ15
INPUT/
OUTPUT
DATA INPUT/OUTPUTS
: Inputs data and commands during CUI write cycles; outputs
data during memory array, status register and identifier code read cycles. Data pins float to
high-impedance when the chip is deselected or outputs are disabled. Data is internally
latched during a pin write cycle. DQ8
DQ15 pins are not used while byte mode (#BYTE =
V
IL
). Then, DQ15 changes A-1address input.
CHIP ENABLE
: Activates the device’s control logic, input buffers, decoders and sense
amplifiers.
#CE-high deselects the device and reduces power consumption to standby levels.
#CE
INPUT
#RESET
INPUT
RESET
: Resets the device internal automation. #RESET-high enables normal operation.
When driven low, #RESET inhibits write operations which provides data protection during
power transitions. Exit from reset mode sets the device to read array mode. #RESET must
be V
IL
during power-up.
INPUT
OUTPUT ENABLE
: Gates the device’s outputs during a read cycle.
#OE
#WE
INPUT
WRITE ENABLE
: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the #WE pulse.
#WP
INPUT
WRITE PROTECT
: When #WP is V
IL
, boot blocks cannot be written or erased. When #WP is
V
IH
, locked boot blocks can not be written or erased. #WP is not affected parameter and main
places device in byte mode (x 8). All data is then input or output on blocks.
#BYTE
INPUT
BYTE ENABLE
: #BYTE V
IL
places the device in byte mode (x 8), All data is then input or
output on DQ0
7, and DQ8
15 float. #BYTE V
IH
places the device in word mode (
×
16),
and turns off the A-1 input buffer.
RY/#BY
OPEN
DRAIN
OUTPUT
READY/#BUSY
: Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, full chip erase, word/byte write or lock-bit
configuration).
RY/#BY-high Z indicates that the WSM is ready for new commands, block erase is
suspended, and word/byte write is inactive, word/byte write is suspended, or the device is
in reset mode.
V
PP
SUPPLY
BLOCK ERASE, FULL CHIP ERASE, WORD/BYTE WRITE OR LOCK-BIT
CONFIGURATION POWER SUPPLY
: For erasing array blocks, writing words/bytes or
configuring lock-bits. With V
PP
≤
V
PPLK
, memory contents cannot be altered. Block erase,
full chip erase, word/byte write and lock-bit configuration with an invalid V
PP
(see DC
Characteristics) produce spurious results and should not be attempted. Applying 12V
±
0.3V to V
PP
during erase/write can only be done for a maximum of 1000 cycles on each
block. V
PP
may be connected to 12V
±
0.3V for a total of 80 hours maximum.
DEVICE POWER SUPPLY
: Do not float any power pins. With V
DD
≤
V
LKO
, all write
attempts to the flash memory are inhibited. Device operations at invalid V
DD
voltage (see
DC Characteristics) produce spurious results and should not be attempted.
V
DD
SUPPLY
V
SS
NC
SUPPLY
GROUND
: Do not float any ground pins.
NO CONNECT
: Lead is not internal connected; it may be driven or floated.
Table 1.
Publication Release Date: October 31, 2002
- 7 -
Revision A3
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