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参数资料
| 型号： | W28J800BT90C |
| 元件分类： | EEPROM |
| 英文描述： | EEPROM |
| 中文描述： | EEPROM的 |
| 文件页数： | 8/51页 |
| 文件大小： | 1468K |
| 代理商： | W28J800BT90C |
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W28J800B/T
7. PRINCIPLES OF OPERATION
The product includes an on-chip WSM to manage block erase, full chip erase, word/byte write and
lock-bit configuration functions. It allows for one hundred percent TTL-level control inputs, fixed power
supplies during block erase, full chip erase, word/byte write and lock-bit configuration, and minimal
processor overhead with RAM-like interface timings.
After initial device power-up or return from reset mode (see Bus Operations section), the device
defaults to read array mode. Manipulation of external memory control pins allow array read, standby
and output disable operations.
Status register and identifier codes can be accessed through the CUI independent of the V
PP
voltage.
High voltage on V
PP
enables successful block erase, full chip erase, word/byte write and lock-bit
configurations. All functions associated with altering memory contents (block erase, full chip erase,
word/byte write, lock-bit configuration, status and identifier codes) are accessed via the CUI and
verified through the status register.
Commands are written using standard microprocessor write timings. The CUI contents serve as input
to the WSM, which controls the block erase, full chip erase, word/byte write and lock-bit configuration.
The internal algorithms are regulated by the WSM, including pulse repetition, internal verification and
margining of data. Addresses and data are internally latched during write cycles. Writing the
appropriate command outputs array data, accesses the identifier codes or outputs status register
data.
Interface software that initiates and polls progress of block erase, full chip erase, word/byte write and
lock-bit configuration can be stored in any block. This code is copied to and executed from system
RAM during flash memory updates. After successful completion, reads are again possible via the
Read Array command. Block erase suspend allows system software to suspend a block erase to
read/write data from/to blocks other than that which is suspend. Word/byte write suspend allows
system software to suspend a word/byte write to read data from any other flash memory array
location.
Data Protection
When V
PP
≤
V
PPLK
, memory contents cannot be altered. The CUI, with two-step block erase, full chip
erase, word/byte write or lock-bit configuration command sequences, provides protection from
unwanted operations even when high voltage is applied to V
PP
. All write functions are disabled when
V
DD
is below the write lockout voltage V
LKO
or when #RESET is at V
IL
. The device’s block locking
capability provides additional protection from inadvertent code or data alteration by gating block erase,
full chip erase and word/byte write operations.
Reference Table 5 for write protection alternatives.
- 8 -
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