参数资料
型号: W39L020P-90Z
厂商: WINBOND ELECTRONICS CORP
元件分类: PROM
英文描述: 256K X 8 FLASH 3.3V PROM, 90 ns, PQCC32
封装: LEAD FREE, PLASTIC, LCC-32
文件页数: 27/29页
文件大小: 294K
代理商: W39L020P-90Z
W39L020
Publication Release Date: June 6, 2005
- 7 -
Revision A7
6.2 Data Protection
The W39L020 is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device
automatically resets the internal state machine in the Read mode. Also, with its control register
architecture, alteration of the memory contents only occurs after successful completion of specific
multi-bus cycle command sequences. The device also incorporates several features to prevent
inadvertent write cycles resulting from VDD power-up and power-down transitions or system noise.
Boot Block Operation
There are four alternatives to set the boot block. Either 16K-byte or 64K-byte in the top/bottom location
of this device can be locked as boot block, which can be used to store boot codes. It is located in the
last 16K/64K bytes or first 16K/64K bytes of the memory with the address range from
3C000/30000(hex) to 3FFFF(hex) for top location or 00000(hex) to 03FFF/0FFFF(hex) for bottom
location.
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the
data for the designated block cannot be erased or programmed (programming lockout), other memory
locations can be changed by the regular programming method.
In order to detect whether the boot block feature is set on the first/last 16K/64K-bytes block or not,
users can perform software command sequence: enter the product identification mode (see Command
Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address
0002(hex) for first(bottom) location or 3FFF2(hex) for last(top) location. If the DQ0/DQ1 of output data
is "1," the 64Kbytes/16Kbytes boot block programming lockout feature will be activated; if the DQ0/DQ1
of output data is "0," the lockout feature will be inactivated and the block can be erased/programmed.
To return to normal operation, perform a three-byte command sequence (or an alternate single-byte
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.
6.2.1
Low VDD Inhibit
To avoid initiation of a write cycle during VDD power-up and power-down, the W39L020 locks out when
VDD < 2.0V (see DC Characteristics section for voltages). The write and read operations are inhibited
when VDD is less than 2.0V typical. The W39L020 ignores all write and read operations until VDD >
2,0V. The user must ensure that the control pins are in the correct logic state when VDD > 2.0V to
prevent unintentional writes.
6.2.2
Write Pulse "Glitch" Protection
Noise pulses of less than 10 nS (typical) on #OE, #CE, or #WE will not initiate a write cycle.
6.2.3
Logical Inhibit
Writing is inhibited by holding any one of #OE = VIL, #CE = VIH, or #WE = VIH. To initiate a write cycle
#CE and #WE must be a logical zero while #OE is a logical one.
6.2.4
Power-up Write and Read Inhibit
Power-up of the device with #WE = #CE = VIL and #OE = VIH will not accept commands on the rising
edge of #WE except 5mS delay (see the power up timing in AC Characteristics). The internal state
machine is automatically reset to the read mode on power-up.
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