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参数资料
| 型号： | W3E32M72S-200SBM |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM, 0.8 ns, PBGA208 |
| 封装： | 16 X 22 MM, PLASTIC, BGA-208 |
| 文件页数： | 12/19页 |
| 文件大小： | 373K |
| 代理商： | W3E32M72S-200SBM |
W3E32M72S-XSBX
2
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
August 2007
Rev. 7
White Electronic Designs Corp. reserves the right to change products or specications without notice.
DENSITY COMPARISONS
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered
coincident with the READ or WRITE command are used
to select the bank and the starting column location for the
burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.
The pipelined, multibank architecture of DDR SDRAMs allows
for concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided, along with a power-
Area
5 x 265mm2 = 1325mm2
352mm2
73%
5 x 66 pins = 330 pins
208 Balls
37%
S
A
V
I
N
G
S
I/O
Count
TSOP Approach (mm)
22.3
11.9
66
TSOP
11.9
66
TSOP
11.9
66
TSOP
11.9
66
TSOP
Area
5 x 125mm2 = 625mm2
352mm2
44%
5 x 60 balls = 300 balls
208 Balls
31%
S
A
V
I
N
G
S
I/O
Count
CSP Approach (mm)
60
FBGA
10.0
60
FBGA
10.0
60
FBGA
10.0
60
FBGA
10.0
12.5
11.9
66
TSOP
60
FBGA
10.0
Actual Size
W3E32M72S-XSBX
22
16
Actual Size
W3E32M72S-XSBX
22
16
saving power-down mode. All inputs are compatible with
the Jedec Standard for SSTL_2. All full drive options
outputs are SSTL_2, Class II compatible.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and
row to be accessed (BA0 and BA1 select the bank, A0-12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be
initialized. The following sections provide detailed
information covering device initialization, register denition,
command descriptions and device operation.
相关PDF资料 |
PDF描述 |
|---|---|
| W3E32M72S-333SBM | 32M X 72 DDR DRAM, 0.7 ns, PBGA208 |
| W3E32M72S-333BI | 32M X 72 DDR DRAM, 0.7 ns, PBGA219 |
| W3E32M72S-250BM | 32M X 72 DDR DRAM, 0.8 ns, PBGA219 |
| W3E32M72S-333BC | 32M X 72 DDR DRAM, 0.7 ns, PBGA219 |
| W3E32M72S-250BC | 32M X 72 DDR DRAM, 0.8 ns, PBGA219 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W3E32M72S-250BC | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR, 2.5V, 250 MHZ, 219 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E32M72S-250BI | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR, 2.5V, 250 MHZ, 219 PBGA, INDUSTRIAL TEMP. - Bulk |
| W3E32M72S-250BM | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR, 2.5V, 250 MHZ, 219 PBGA, MIL-TEMP. - Bulk |
| W3E32M72S-250SBC | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR, 2.5V, 250 MHZ, 208 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E32M72S-250SBI | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR, 2.5V, 250 MHZ, 208 PBGA, INDUSTRIAL TEMP. - Bulk |
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