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参数资料
| 型号： | W3E32M72S-200SBM |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM, 0.8 ns, PBGA208 |
| 封装： | 16 X 22 MM, PLASTIC, BGA-208 |
| 文件页数： | 14/19页 |
| 文件大小： | 373K |
| 代理商： | W3E32M72S-200SBM |
W3E32M72S-XSBX
4
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
August 2007
Rev. 7
White Electronic Designs Corp. reserves the right to change products or specications without notice.
A0-12
BA0-1
CK0#
CK
#
CAS
#
DQ0
DQ15
CKE0
CKE
CS0
#
CS
#
DQML0
DQML
DQMH0
DQMH
RAS1
#
WE1
#
CAS1
#
DQ0
DQ15
WE
#
U1
RAS
#
A0-12
BA0-1
CK1#
CK
#
CAS
#
DQ16
DQ31
RAS0
#
WE0
#
CAS0
#
DQ0
DQ15
WE
#
U0
RAS
#
CKE1
CKE
CS1
#
CS
#
DQML1
DQML
DQMH1
DQMH
RAS2
#
WE2
#
CAS2
#
DQ0
DQ15
WE
#
U2
RAS
#
A0-12
BA0-1
CK2#
CK
#
CAS
#
DQ32
DQ47
CKE2
CKE
CS2
#
CS
#
DQML2
DQML
DQMH2
DQMH
RAS3
#
WE3
#
CAS3
#
DQ0
DQ15
WE
#
U3
RAS
#
A0-12
BA0-1
CK3
#
CK
#
CAS
#
DQ48
DQ63
CKE3
CKE
CS3
#
CS
#
DQSL3
DQSL
DQSH3
DQSH
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Y
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Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
CK3
CK
VREF
DQSL2
DQSL
DQSH2
DQSH
VREF
DQSL1
DQSL
DQSH1
DQSH
VREF
DQSL0
DQSL
DQSH0
DQSH
VREF
CK2#
CK
CK1
CK
CK0
CK
VREF
DQML3
DQML
DQMH3
DQMH
RAS4
#
WE4
#
CAS4
#
DQ0
DQ15
WE
#
U4
RAS
#
A0-12
BA0-1
CK4
#
CK
#
CAS
#
DQ64
DQ79
CKE4
CKE
CS4
#
CS
#
DQSL4
DQSL
DQSH4
DQSH
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
CK4
CK
VREF
DQML4
DQML
DQMH4
DQMH
FIG. 2 FUNCTIONAL BLOCK DIAGRAM
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a
predened manner. Operational procedures other than
those specied may result in undened operation. Power
must rst be applied to VCC and VCCQ simultaneously, and
then to VREF (and to the system VTT). VTT must be applied
after VCCQ to avoid device latch-up, which may cause
permanent damage to the device. VREF can be applied any
time after VCCQ but is expected to be nominally coincident
with VTT. Except for CKE, inputs are not recognized as
valid until after VREF is applied. CKE is an SSTL_2
input but will detect an LVCMOS LOW level after VCC is
applied. After CKE passes through VIH, it will transition to
an SSTL_2 signal and remain as such until power is cycled.
Maintaining an LVCMOS LOW level on CKE during power-
up is required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until driven
in normal operation (by a read access). After all power
supply and reference voltages are stable, and the clock
is stable, the DDR SDRAM requires a 200μs delay prior
to applying an executable command.
Once the 200μs delay has been satised, a DESELECT
or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REGISTER command should be issued for
the extended mode register (BA1 LOW and BA0 HIGH)
to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL and to program the operating
parameters. Two-hundred clock cycles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must
be performed (tRFC must be satised.) Additionally, a LOAD
MODE REGISTER command for the mode register with
the reset DLL bit deactivated (i.e., to program operating
parameters without resetting the DLL) is required.
Following these requirements, the DDR SDRAM is ready
for normal operation.
相关PDF资料 |
PDF描述 |
|---|---|
| W3E32M72S-333SBM | 32M X 72 DDR DRAM, 0.7 ns, PBGA208 |
| W3E32M72S-333BI | 32M X 72 DDR DRAM, 0.7 ns, PBGA219 |
| W3E32M72S-250BM | 32M X 72 DDR DRAM, 0.8 ns, PBGA219 |
| W3E32M72S-333BC | 32M X 72 DDR DRAM, 0.7 ns, PBGA219 |
| W3E32M72S-250BC | 32M X 72 DDR DRAM, 0.8 ns, PBGA219 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W3E32M72S-250BC | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR, 2.5V, 250 MHZ, 219 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E32M72S-250BI | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR, 2.5V, 250 MHZ, 219 PBGA, INDUSTRIAL TEMP. - Bulk |
| W3E32M72S-250BM | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR, 2.5V, 250 MHZ, 219 PBGA, MIL-TEMP. - Bulk |
| W3E32M72S-250SBC | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR, 2.5V, 250 MHZ, 208 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E32M72S-250SBI | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR, 2.5V, 250 MHZ, 208 PBGA, INDUSTRIAL TEMP. - Bulk |
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